Sony MDS-JA555ES Service Manual ▷ View online
61
IC405 SN74HC153ANS (DIGITAL BOARD)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2G
2C3
2C2 2C1 2C0
2Y
VCC
2C3
2C2 2C1 2C0
STROBE
2G
OUTPUT
2Y
A
SELECT
DATA INPUTS
B
B
A
A
B
B
A
A
1G
1C3 1C2
1C1 1C0
1Y
STROBE
1G
B
SELECT
1C3 1C2
1C1
1C0
OUTPUT
1Y
GND
DATA INPUTS
IC240 LA5632 (PW BOARD)
IC250 LB1641 (PW BOARD)
1
–
+
12
DELAY
CIRCUIT
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
V
CC
ANA5
SYS3.3
B.BAK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
IC270 M5293L (PW BOARD)
2
5
5k
+
–
27k
OVERCURRENT
LIMITTER
OVERHEAT
PROTECTION
REFERENCE
VOLTAGE
GND
ON/OFF
IN
REFERENCE
VOLTAGE
VOLTAGE
OUT
3
4
1
62
Pin No.
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I
I
—
I
O
I
O
O
I
I
O
O
O
O
O
O
O
I
I
O
I
I
O
I
O
I
O
Description
RF signal input (I) that is supplied form the optical pickup detector and has already been I-V converted
RF signal input (J) that is supplied form the optical pickup detector and has already been I-V converted
Middle point voltage (+1.65 V) generation output
Signal input from optical pick-up detector (A to F)
Light amount monitor input from laser diode of optical pick-up
Laser amplifier output to automatic power control circuit
Reference voltage input for setting laser power from CXD2656R (IC121)
Ground
Temperature sensor connection pin
Reference voltage output for temperature sensor
Write data signal input from CXD2656R (IC121)
Serial clock signal input from CXD2656R (IC121)
Serial latch signal input from CXD2656R (IC121)
Standby signal input
Control signal input of center frequency for internal circuit filter (BPF22, BPF3T, EQ) from CXD2656R
(IC121)
Reference voltage output Not used in this system (Blank terminal)
Input pin for setting center frequency of internal circuit filter (EQ)
Input pin for setting center frequency of internal circuit filter (BPF3T)
Power supply (+33 V)
Input pin for setting center frequency of internal circuit filter (BPF22)
Tracking error signal output to CXD2656R (IC121)
Connection pin of capacitor for low path filter of sled error
Sled error signal output to CXD2656R (IC121)
ADIP FM signal output
Inputs ADIP FM signal by AC coupling
Connection pin of external capacitor for ADIP AGC
ADIP dual FM signal output to CXD2656R (IC121) (2205 kHz ± 1 kHz)
Auxiliary signal (I3 signal/temperature signal) output to CXD2656R (IC121)
Focus error signal output to CXD2656R (IC121)
Light amount signal (ABCD) output to CXD2656R (IC121)
Bottom hold signal output of light amount signal (RF/ABCD) to CXD2656R (IC121)
Peak hold signal output of light amount signal (RF/ABCD) to CXD2656R (IC121)
Playback EFM RF signal output to CXD2656R (IC121)
Connection pin of RF AGC circuit external capacitor
Inputs RF signal by AC coupling
Output terminal to user’s comparator. Not used. (Blank terminal)
Inverted input terminal from user’s comparator. Not used. (Fixed to “L”)
The terminal to which external capacitor to cut off low frequency range of the ADIP amplifier, is going to be
connected.
Output terminal to user’s operational amplifier. Not used. (Blank terminal)
Inverted input terminal from user’s operational amplifier. Not used. (Fixed to “L”)
Output pin of RF signal
Inputs MO RF signal by AC coupling
Output pin of MO RF signal
Pin Name
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
VCC
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
6-22. IC PIN FUNCTION DESCRIPTION
• BD BOARD IC101 CXA2523AR (RF AMPLIFIER, FOCUS/TRACKING ERROR AMPLIFIER)
63
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
Description
Focus OK signal output to system controller (IC800)
Outputs “H” when focus is set (“L”: NG)
Track jump detection signal output to system controller (IC800)
Busy monitor signal output to system controller (IC800)
Spindle servo lock status monitoring signal output to system controller (IC800)
Inputs write data signal from system controller (IC800)
Inputs serial clock signal from system controller (IC800)
Inputs serial latch signal from system controller (IC800)
Outputs read data signal to system controller (IC800)
Outputs internal status (SENSE) signal to system controller (IC800)
Inputs reset signal input from system controller (IC800) “L”: Reset
Sub code Q sync (SCOR) output to system controller (IC800)
Outputs “L” every 133 msec. Outputs “H” mostly
Outputs digital-in U-bit CD format sub code Q sync (SCOR) to system controller (IC800)
Outputs “L” every 133 msec. Outputs “H” mostly
Laser power switching signal input from system controller (IC800)
“L”: Playback, “H”: Recording
Interrupt status output to system controller (IC800)
Recording data output enable signal input from system controller (IC800).
Transmission timing of the write signal is input. (Used also as ON/OFF of magnetic head)
System clock (1024Fs = 451584 MHz) input
System clock (1024Fs = 451584 MHz) output. Not used in this system (Blank terminal)
System clock frequency setting input.
“L”: 451584 MHz, “H”: 22.5792 kHz
Recording system digital audio signal input (for digital optical -1/2 input and coaxial input)
Recording system digital audio signal input. Not used (Fix at “L”)
Playback system digital audio signal output (for digital optical output and coaxial input)
Serial data input Not used (Fix at “L”)
L/R sampling clock signal input (44.1 kHz)
Not used in this system (Fixed at “L”)
Bit clock signal input of serial input/output (2.8224 kHz)
Not used in this system (Fixed at “L”)
Recording data signal input from CXD8512Q (IC301)
Playback data signal output from CXD8512Q (IC301)
L/R sampling clock signal output (44.1 kHz) to CXD8512Q (IC301) and CXD8762Q (IC501)
Bit clock signal output of serial input/output data (44.1 kHz) to CXD8512Q (IC301) and CXD8762Q (IC501)
11.2896 MHz clock signal output Not used (Blank terminal)
Power supply (+5 V) (Digital)
Address signal output to D-RAM (IC124)
Address signal output to external D-RAM Not used (Blank terminal)
Address signal output to D-RAM (IC124)
Pin Name
MNT0 (FOK)
MNT1 (SHOCK)
MNT2 (XBUSY)
MNT3
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DATAI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
• BD BOARD IC121 CXD2656R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR,
EFM/ACIR ENCODER/DECODER, SHOCK-PROOF REMOTE CONTROLLER,
ATRAC ENCODER/DECODER)
EFM/ACIR ENCODER/DECODER, SHOCK-PROOF REMOTE CONTROLLER,
ATRAC ENCODER/DECODER)
* I (S) of I/O is schmitt input, I (A) is analog input, O (3) is 3-state output, O (A) is analog output
64
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
I/O
O
—
O
O
O
O
O
I/O
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
Description
Address signal output to external D-RAM Not used (Blank terminal)
Ground (Digital)
Output enable signal output to D-RAM (IC124) “L”: Active
Column address strobe signal output to D-RAM (IC124) “L”: Active
Address signal output to D-RAM (IC124)
Low address strobe signal output to D-RAM (IC124) “L”: Active
Write enable signal output to D-RAM (IC124) “L”: Active
Bi-directional data bus with D-RAM (IC124)
Input to digital-in PLL oscillation from external VCO. Not used (Fix at “L”)
Playback EFM full-swing output
Playback EFM asymmetry comparate voltage input
Power supply (+3.3 V) (Analog)
Constant current input to playback EFM asymmetry circuit
Playback EFM RF signal input from CXA2523AR (IC101)
Ground (+3.3 V) (Analog)
Phase comparator output to master clock of the master PLL of the record/playback EFM system
Filter input to master clock of the master PLL of the record/playback EFM system
Filter output to master clock of the master PLL of the record/playback EFM system
Internal VCO control voltage input to the master PLL of the record/playback EFM system
Peak hold signal input of light amount signal (RF/ABCD) from CXD2523AR (IC101)
Bottom hold signal input of light amount signal (RF/ABCD) from CXD2523AR (IC101)
Light amount signal (ABCD) from CXD2523AR (IC101)
Focus error signal input from CXD2523AR (IC101)
Auxiliary signal (I3 signal/temperature signal) output from CXD2523AR (IC101)
Middle point voltage (+1.65 V) output from CXD2523AR (IC101)
Monitor output of A/D converter input signal. Not used in this system (Blank terminal)
Power supply (+3.3 V) (Analog)
A/D converter operation range upper limit voltage input. (Fixed to “H”)
A/D converter operation range lower limit voltage input. (Fixed to “L”)
Ground (Analog)
Sled error signal input from CXD2523AR (IC101)
Tracking error signal input from CXD2523AR (IC101)
Connected to power line (+3.3 V)
Error signal input to laser automatic power control. Not used in this system (Fixed to “H”)
ADIP dual FM signal input from CXD2523AR (IC101) (22.05 kHz ± 1 kHz)
Filter f0 control signal output to CXD2523AR (IC101)
Serial latch signal output to CXD2523AR (IC101)
Serial clock signal output to CXD2523AR (IC101)
Write data signal output to CXD2523AR (IC101)
Control signal output for reference voltage generation circuit of laser automatic power control to
CXD2523AR (IC101)
PWM signal output for laser automatic power control
Not used in this system (Blank terminal)
Tracking servo drive PWM signal output to BH6511FS (IC152) (-)
Pin Name
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
D1
D0
D2
D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
LDDR
TRDR
* I (S) of I/O is schmitt input, I (A) is analog input, O (3) is 3-state output, O (A) is analog output
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