Sony MDS-JA30ES Service Manual ▷ View online
— 66 —
Pin No.
I/O
Description
Pin Name
45
46 to 48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SRC TEST
—
DAMUTE
STB
OUTSW
INSW
—
LDIN
LDOUT
HUP
HDWN
37RST
HUPS
HDOWNS
REC/PB
VCC
—
VSS
—
MOD
SCTX
FG
FOK
SHCK
WRPWR
DIG-RST
—
SDA
SCL
SENS
PROTECT
REFLECT
LDON
LIMIT-IN
O
—
O
O
I
I
—
O
O
O
O
O
I
I
O
—
—
—
—
O
O
I
I
I
O
O
—
I/O
O
I
I
I
O
I
The second reset signal output from sampling rate converter
Not used
D/A line mute output “L”:Active
Strobe signal output to power supply circuit When power is ON:“H”, When standby:“L”
Detection input from loading out detection switch
Detection input from loading in detection switch
Not used
Loading motor control output
Magnetic head up/down control output
Reset signal output to ATRAC encoder/decoder “L”:Reset
Detection input from magnetic head up detection switch
Detection input from magnetic head down detection switch
Recording/playback selection signal output to CXD2535CR
When recording:“H”, when playing back:“L”
Power supply (+5V)
Not used
Ground
Not used
Laser modulation switching signal output
During playback power: “L”, During stop:“H”
During recording power:
Write data transmission timing output to ATRAC encoder/decoder
Used also as magnetic head ON/OFF output
FG detection signal output from spindle motor driver
FOK signal input from CXD2535CR
“H” is input when focus is set
Track jump detection signal input from CXD2535CR
Laser power switching signal output to optical pick-up and CXD2535CR
Digital reset signal output
Not used
Input/output of data signal with EEPROM
Clock signal output to EEPROM
Internal status (SENSE) input from CXD2535CR
Recording prevention tab detection input from protect detection switch
When protect is ON:“H”
Disc reflection rate detection input from reflect detection switch
When low reflection rate disc is used:“H”
Laser ON/OFF control output “H”:Laser ON
Detection input from limit-in switch
When sled limit in:“L”
0.5S
2S
— 67 —
Pin No.
I/O
Description
Pin Name
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CSET0
CSET1
POWER
PLAY
—
REC
—
PAUSE
—
KEY1
KEY2
KEY3
KEY0
TIMER
SORCE
AVSS(AGND)
DVOL
VREF(+5V)
AVCC
DF
I
I
O
O
—
O
—
O
—
I
I
I
I
I
I
—
I
I
—
O
Destination setting pin
POWER LED drive output
PLAY (
() LED drive output
Not used
REC (
r) LED drive output
Not used
PAUSE (
P) LED drive output
Not used
Key input (A/D)
Timer recording/playback/OFF switching input “L”:Playback, “H”:Recording, “M”:OFF
Input signal (analog/digital input) selection signal input
Analog ground
Digital input level volume input (A/D)
A/D reference voltage input (+5V)
Analog power supply (+5V)
FILTER LED drive output
— 68 —
Pin No.
I/O
Description
Pin Name
• IC203 Digital Audio Interface Receiver (LC89051V-TLM)/DIG board
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DIN1
DIN2
E/DOUT
VDD
R
VIN
VCO
GND
CKSEL
XMODE
AVOCK
TST1
TST2
SCLK
XLAT
SWDT
SRDT
DQSY
CKOUT
FS128
BCK
LRCK
DATAOUT
ERROR
I
I
O
—
I
I
O
—
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
Data input with built-in amplifier (responding to the coaxial optical module)
Data input (responding to the optical module) (Not used)
Emphasis, input bi-phase, validity flag output (Not used)
Power supply (+5V)
VCO gain control input
VCO freerunning frequency setting input
LPF setting of PLL
Ground
System clock select input (384fs, 512fs) (Fixed at “H”)
Reset input
Clock input for preventing PLL lock failure
Test input (Normally “L”)
Microcomputer IF clock input
Microcomputer IF latch/chip enable input
Microcomputer IF write data input
Microcomputer IF read data output
Microcomputer IF Sub-Q sync and ID sync output
VCO clock output (freerunning, 384fs, 512fs)
128fs clock output (Not used)
Bit clock output
L/R clock output
Audio data output
PLL lock error mute output
— 69 —
Pin No.
I/O
Description
Pin Name
• IC206 Shock-Proof Memory Controller, ATRAC Encoder/Decoder (CXD2537R)/DIG board
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 to 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 to 47
VDD
SWDT
SCK
XLAT
SRDT
SENSE
SCMD0
SCMD1
XINT
RCPB
WRMN
TX
VSS
SICK
IDSL
XILT
XRST
TS0 to TS3
EXIR
SASL
SNGLE
VSS
AIRCPB
XRQ
ADTO
ADTI
XALT
ACK
AC2
LCHST
EXE
MUTE
OSCO
OSCI
VSS
ATT
F86
DOUT
ADIN
ABCK
ALRCK
SA2 to SA0
—
I
I
I
O/Z
O/Z
I
I
O
I
I
I
—
I
I
I
I
I
I
I
I
—
O
O
I
O
I
I
I
I/O
I/O
I/O
O
I
—
I/O
O
O
I
O
O
O
Power supply (+5V)
Input of write data signal from system controller
Input of serial clock signal from system controller
Input of serial latch signal from system controller
Output of read data signal to system controller
Internal status (SENSE) output (Not used)
Serial command control mode input (Fixed at “H”)
Interrupt status output
Recording/playback switching input “L”: Recording mode (Fixed at “L”)
Write/monitor mode switching signal input “H”: Monitor mode (Fixed at “L”)
Write data transmission timing input
Also used as magnetic field head ON/OFF output
Ground
Chip reservation pin (Fixed at “L”)
Chip reservation pin (Fixed at “H”)
Input of reset signal from system controller Reset: “L”
Test pin (Fixed at “L”)
Chip reservation pin (Fixed at “L”)
Block selection in single use “L”: ATRAC “H”: RAM controller (Fixed at “L”)
Normally fixed at “L” Fixed at “H” when used as ATRAC or RAM controller for single (Fixed at “L”)
Ground
Output of ATRAC and external audio block recording/playback mode signal (Not used)
ATRAC I/F data request signal output (Not used)
ATRAC decode data signal input (Not used)
ATRAC encode data signal output (Not used)
ATRAC I/F XALT signal input (Not used)
ATRAC I/F ACK signal input (Not used)
ATRAC I/F C2PO signal input (Not used)
ATRAC I/F Lch start data signal input/output (Not used)
ATRAC I/F EXE signal input/output (Not used)
ATRAC I/F MUTE signal input/output (Not used)
Clock output (45 MHz) (Not used)
Clock input (45 MHz)
Ground
ATRAC I/F ATT signal input/output (Not used)
ATRAC block 11.6 msec timing signal output (Not used)
Output of audio data signal to D/A converter
Input of recording signal from A/D converter
Bit clock signal output
L/R clock output
Address signal output (Not used)
* O/Z: In case of no output data, it becomes high impedance
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