Sony MDS-JA30ES Service Manual ▷ View online
— 62 —
I/O
Description
Pin Name
• IC121 Digital Signal Processor, Digital Servo Processor, EFM/ACIRC Encoder/Decoder (CXD2535CR)/BD board
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FS256
FOK
DFCT
SHCK
SHCKEN
WRPWR
DIRC
SWDT
SCLK
XLAT
SRDT
SENS
ADSY
SQSY
DQSY
XRST
TEST4
CLVSCK
TEST5
DOUT
DIN
FMCK
ADER
REC
DVSS
DOVF
DODT
DIDT
DTI
DTO
C2PO
BCK
LRCK
XTAO
XTAI
MCLK
XBCK
DVDD
WDCK
RFCK
O
O
O
O
I
I
I
I
I
I
O
O (3)
O
O
O
I
I
O
I
O
I
O
O
I
—
I
I
O
I
O (3)
O
O
O
O
I
O
O
—
O
O
11.2896 MHz clock output (MCLK) (Not used)
Output of FOK signal to system controller
Outputs “H” when focus is set
Outputs defect ON/OFF switching signal to ATRAC encoder/decoder
Outputs track jump detection signal to system controller
Track jump detection enable input (Not used) (Fixed at “H”)
Inputs laser power switching signal from system controller
Disc drive recording/playback switching signal input (Fixed at “H”)
Inputs write data signal from system controller
Inputs serial clock signal from system controller
Inputs serial latch signal from system controller
Outputs read data signal to system controller
Outputs internal status (SENSE) to system controller
ADIP sync signal output (Not used)
Output subcode Q sync (SCOR) to system controller
Outputs “L” every 13.3 msec Outputs “H” at all most mostly
Outputs digital-in U-bit CD format subcode Q sync (SCOR) to system controller
Outputs “L” every 13.3 msec Outputs “H” at all most mostly
Inputs reset signal from system controller Reset: “L”
Test input (Fixed at “L”)
Not used
Test input (Fixed at “L”)
Digital audio signal output (For optical output)
Digital audio signal input (For optical input) (Not used)
ADIP FM demodulation clock signal output
ADIP CRC flag output “H”:Error
Input of recording/playback switching signal from system controller
Recording: “H” Playback: “L”
Ground (Digital)
Digital audio output validity flag input (Fixed at “L”)
Input of 16bit data for digital audio output
Output of 16bit data for digital audio input to ATRAC encoder/decoder
Input of recording audio data signal from ATRAC encoder/decoder
Output of playback audio data signal to ATRAC encoder/decoder
Outputs C2PO signal to ATRAC encoder/decoder (Output indicating data error status)
Playback: C2PO (“H”) Digital recording: Digital-in-Vflag Analog recording: “L”
Outputs bit clock signal (2.8224 MHz) (MCLK)
Outputs L/R clock signal (44.1 kHz) (MCLK)
System clock (512 fs=22.5792 MHz) signal output
Input of system clock (512fs=22.5792 MHz) signal input
MCLK clock (22.5792 MHz) signal output (Not used)
Pin 32 (BCK) inversion output (Not used)
Power supply (+5V) (Digital)
WDCK clock (88.2 kHz) signal output (MCLK)
RFCK clock (7.35 kHz) signal output (MCLK)
* (3) of I/O is 3-state output, (A) is analog output.
— 63 —
Pin No.
I/O
Description
Pin Name
• Abbreviation
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
PLL : Phase Locked Loop
* (3) of I/O is 3-state output, (A) is analog output.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
WFCK
GTOP
GFS
XPLCK
EFMO
RAOF
MVCI
TEST2
DIPD
DVSS
DICV
DIFI
DIFO
AVDD
ASYO
ASYI
BIAS
RFI
AVSS
CLTV
PCO
FILI
FILO
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
TEST3
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
O
O
O
O
O
O
I
I
O (3)
—
I (A)
I (A)
O (A)
—
O
I (A)
I (A)
I (A)
—
I (A)
O (3)
I (A)
O (3)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
I (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (A)
WFCK clock (7.35 kHz) signal output
(Playback: EFM decoder PLL Recording: EFM encoder PLL)
“H”: Opens playback EFM frame sync protection window
“H”: Playback EFM sync and interpolation protection timing match
EFM decoder PLL clock output (98 fs=4.3218 MHz)
Falling edge and EFM signal edge match
EFM signal output (Recording)
Internal RAM overflow detection signal output (decoder monitor output)
Outputs “H” when the disc rotation exceeds ±4F jitter margin during playback
Digital-in PLL oscillation input (Not used) (Fixed at “L”)
Test pin (Fixed at “L”)
Digital-in PLL phase comparison output
Internal VCO: (Frequency: Low n “H”) External VCO: (Frequency: Low n “L”)
Ground (Digital)
Digital-in PLL internal VCO control voltage input
Filter input when digital-in PLL internal VCO is used
Filter output when digital-in PLL internal VCO is used (Not used)
Power supply (+5V) (Analog )
Playback EFM full-swing output (L=VSS, H=VDD)
Playback EFM asymmetry comparate voltage input
Playback EFM asymmetry circuit constant current input
Inputs playback EFM RF signal from RF amplifier
Ground (Analog )
Decoder PLL master clock PLL VCO control voltage input
Decoder PLL master clock PLL phase comparison output
Decoder PLL master clock PLL filter input
Decoder PLL master clock PLL filter output
Inputs peak hold signal for light amount signal from RF amplifier
Inputs bottom hold signal for light amount signal from RF amplifier
Light amount signal from RF amplifier
Input of focus error signal from RF amplifier
Input of auxiliary signal from RF amplifier
Input of middle point voltage (+2.5V) from RF amplifier
A/D converter input signal monitor output
Test input (Fixed at “L”)
Power supply (+5V) (Analog)
A/D converter operation range upper limit voltage input (Fixed at “H”)
A/D converter operation range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Input of sled error signal from RF amplifier
Input of tracking error signal from RF amplifier
Auxiliary input pin 2 (Fixed at “L”)
Connected to ground
Laser APC input (Fixed at “L”)
— 64 —
Pin No.
I/O
Description
Pin Name
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TEST1
ADFG
TS25
LDDR
TRDR
TFDR
FFDR
DVDD
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
DCLO
DCLI
XDCL
OFTRK
COUT
DVSS
I
I
I
O
O
O
O
—
O
O
O
O
O
O
O
I
O
O
O
—
Test pin (Fixed at “L”)
Input of ADIP dual FM signal from RF amplifier (22.05 kHz ±1 kHz)
(TTL Schmidt input)
Test pin (Fixed at “L”)
Laser APC signal output
Tracking servo drive signal output (–)
Tracking servo drive signal output (+)
Focus servo drive signal output (+)
Power supply (+5V) (Digital)
Focus servo drive signal output (–)
176.4 kHz clock signal output (MCLK) (Not used)
Sled servo drive signal output (–)
Sled servo drive signal output (+)
Spindle servo drive signal output (–)
Spindle servo drive signal output (+)
Not used normally
Not used normally (Fixed at “H”)
Not used normally
Off track signal output (Not used)
Traverse count signal output (Not used)
Ground (Digital)
— 65 —
Pin No.
I/O
Description
Pin Name
• IC202 System Controller (M30610EC-1086CFP)/DIG board
1, 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21, 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
—
JOG0
JOG1
SQSY
REMOCON
—
BYTE
CNVSS
XIN-T
XOUT-T
SYSTEM-RST
XOUT
GND
XIN
+5V
MNI
—
POWER DOWN
DQSY
—
XINT
04LAT
62RST
95RST
95LAT
ADRST
ADLAT
XLATCH
SWDT
SRDT
SCLK
—
FLDATA
—
FLCLK
FLCS
—
COAX/XOPT
OPT1/XOPT2
DIN/XMD
EROR
SRCRST
—
I
I
I
I
—
I
—
I
O
I
O
—
I
—
I
—
I
I
—
I
O
O
O
O
O
O
O
O
I
O
—
O
—
O
O
—
O
O
O
I
O
AMS jog signal input
ATP address sync or sub code Q sync (SCOR) input from CXD2535CR
“L” is input every 13.3 msec Mainly “H”
Remote control signal interruption input
Not used
Data bus switching signal input “L”:Single chip mode (Fixed at “L”)
Ground
Sub clock input (37.768 kHz)
Sub clock output (32.768 kHz)
System reset input “L”:Reset
Main clock output (10 MHz)
Ground
Main clock input (10 MHz)
Power supply (+5V)
Not used
Power down detection signal input “L”:Power down
Digital-in U-bit CD format sub code Q sync (SCOR) input from CXD2535CR
“L” is input every 13.3 msec Mainly “H”
Not used
Interruption status input from ATRAC encoder/decoder
Data read signal output to sampling rate converter, digital filter
“L”:Active
Reset signal output to D/A converter “L”:Reset
Reset signal output to CXD8595Q “L”:Reset
Transmission data latch signal output to CXD8595Q
Reset signal output to A/D converter “H”:Reset
Latch signal output to A/D converter
Serial data latch signal output
Write data signal input to serial bus
Read data signal input from serial bus
Clock signal output to serial bus
Not used
Transmission data clock output to FL driver
Not used
Transmission data clock output to FL driver
Transmission data chip select output to FL driver
Not used
Digital-in select signal output “L”:Optical input, “H”:Coaxial input
Digital-in select signal output “L”:OPT2, “H”:OPT1
Digital-out select signal output “L”:MD, “H”:Digital in through
Digital-in error signal input
Reset signal output to sampling rate converter, digital filter “L”:Reset
• Abbreviation
FL : Fluorescent indicator tube
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