Sony MDS-J3000 / MDS-J3000ES Service Manual ▷ View online
— 62 —
— 61 —
6-10. IC BLOCK DIAGRAMS — MAIN SECTION —
1
–
+
12
DELAY
CIRCUIT
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
V
CC
ANA5
SYS3.3
BACK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11
2
5
5k
+
–
27k
OVERCURRENT
LIMITTER
OVERHEAT
PROTECTION
REFERENCE
VOLTAGE
GND
ON/OFF
IN
REFERENCE
VOLTAGE
VOLTAGE
OUT
3
4
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
INRP
INRM
REFI
AVDD
AVSS
APD
NU
NU
TEST1
LRCK1
BCK1
ADDT
V35A
VSS1 (LF)
MCKI
DPD
VSS2(LF)
INIT
MODE
SHIFT
LATCH
256CK
V35D
VSS2
512CK
BCK2
DADT
LRCK2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INLP
INLM
REFO
LVSS
LVDD
AVSS(LF)
NU
NU
VSS1(LF)
TEST3
TEST2
VSS1
VDD1
VDD1
VDD2
L1
AVDDL
L2
AVSSL
XVSS
XIN
XOUT
XVDD
AVSSR
R2
AVDDR
R1
VDD2
MODULATOR
MODULATOR
DECIMATION
FILTER
DECIMATION
FILTER
LOW CUT
FILTER
LOW CUT
FILTER
VOLTAGE
REFERENCE
I/O
I/O
ATT
PLM
OVER
SAMP
FILTER
MOIZE
SHAPER
CPU
INTERFACE
+
–
+
–
ATT
PLM
OVER
SAMP
FILTER
NOIZE
SHAPER
IC304 CXD8607N
IC356 SN74HC153AN
16
1
2
3
4
5
6
7
8
15
14
13
12
2C3
2C2
B
A
B
A
2C1
2C0
2Y
1C3
1C2
1C1
1C0
1Y
V
CC
2C3
2C2
2C1
2C0
DATA INPUTS
DATA INPUTS
STROBE
2G
STROBE
1G
B
SELECT
1C3
1C2
1C1
1C0 OUTPUT
1Y
GND
A
SELECT
OUTPUT
2Y
2G
11
10
9
1G
B
A
B
A
10
9
8
7
6
5
4
3
PRE
DRIVER
INPUT LOGIC BLOCK
GND
OUT1
P1
VZ
IN1
IN2
V
CC
1
V
CC
2
P2
OUT2
2
1
MDS-J3000/J3000ES
–
+
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
13.2k
2.35k
2.35k
13.2k
13.2k
V
CC
10
11
12
13
22
21
20
19
36
35
34
33
32
16
17
18
14
15
–
+
–
+
–
+
–
+
+
–
–
+
–
+
+
–
+
–
V
EE
LINE02
PMUTE
LINE01
MUTE
LINE/MIC
+D/A1
+D/A1
+D/AO1
LP1N1
LPOUT1
GND1
LPOUT2
LPIN2
D/AO2
–D/A2
+D/A2
V
CC
V
DD
–
+
LINE1
V
EE
MIC1
SW01
SWI1
–A/D1
INV1
+A/D1
A/DREF
VREF
+A/D2
INV2
–A/D2
SWI2
SWO2
MIC2
GND2
LINE2
IC302 CXA8065S
42
41
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
24
23
22
32
1
CIREF
ANALOG
VOLUME
CONTROL
CIRCUIT
CONSTANT
CONTROL
CIRCUIT
ECL
SWITCHING
CIRCUIT
ECL
SWITCHING
CIRCUIT
LOGIC
REFERENCE
VOLTAGE
CIRCUIT
NC
AGND
NC
IOR–
IOR+
C5
C6
C7R
AVEES
AVEES
C4R
C3
DVEE
C1R
DGND
1N1–R
1N1+R
NC
1N2+R
1N2–R
RIREF
VREF
VCNT
AGND
AV
CC
NC
IOL–
IOL+
C7L
AVEES
AVEES
C4L
DV
EE
DV
CC
C1L
DGND
1N1–L
1N1+L
NC
1N2+L
1N2–L
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
11
CONSTANT
CONTROL
CIRCUIT
IC303 CXA8055M
IC351 LB1641
IC901 LA5620
IC902 M5293L
— 63 —
6-11. IC PIN FUNCTIONS
• IC101 RF Amplifier (CXA2523R)
Pin No.
Pin Name
I/O
Function
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2650R
Serial clock input from the CXD2650R
Latch signal input from the CXD2650R
“L”: Latch
Stand by signal input
“L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2650R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2650R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2650R
FM signal output of ADIP
ADIP signal comparator input
ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2650R
I
3
signal/temperature signal output to the CXD2650R (Switching with a serial command)
Focus error signal output to the CXD2650R
Light amount signal output to the CXD2650R
RF/ABCD bottom hold signal output to the CXD2650R
RF/ABCD peak hold signal output to the CXD2650R
RF equalizer output to the CXD2650R
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit
The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
— 64 —
• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2650R)
Function
Pin No.
Pin Name
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29 to 32
33
34 to 38
39
40
41
42
43
44
45
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DVDD
DVSS
DIN
DOUT
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
—
—
I
O
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
FOK signal output to the system control
“H” is output when focus is on
Track jump detection signal output to the system control
Monitor 2 output to the system control
Monitor 3 output to the system control
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec
Almost all, “H” is output
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
+3V power supply (Digital)
Ground (Digital)
Digital audio input (Optical input)
Digital audio output (Optical output)
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM (Not used)
CAS signal output for DRAM (Not used)
Address output for DRAM (Not used)
RAS signal output for DRAM (Not used)
Write enable signal output for DRAM (Not used)
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
— 65 —
Function
Pin No.
Pin Name
I/O
46
47
48, 49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PDO
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
LDDR
TRDR
Data input/output for DRAM (Not used)
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the clock playback analog PLL of the playback EFM
(Not used)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523R
Light amount signal bottom hold input from the CXA2523R
Light amount signal input from the CXA2523R
Focus error signal input from the CXA2523R
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523R
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523R
Tracking error signal input from the CXA2523R
Auxiliary A/D input (Fixed at “L”)
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523R (22.05 ± 1 kHz)
Filter f
0
control output to the CXA2523R
Control latch output to the CXA2523R
Control clock output to the CXA2523R
Control data output to the CXA2523R
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
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