Sony MCE-SV7 / MHC-SV7AV Service Manual ▷ View online
36
MCE-SV7
•
VMP BOARD IC505 CL680T-D1 (MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used (open)
2
VSS
—
Ground terminal
3
CD-BCK
I
CD decode bit clock signal (2.8224 MHz) input from the CXD3068Q (IC101)
4
CD-DATA
I
CD decode data input from the CXD3068Q (IC101)
5
CD-LRCK
I
CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3068Q (IC101)
6
CD-C2PO
I
CD decode C2 error data input from the CXD3068Q (IC101)
7 to 9
NC
O
Not used (open)
10 to 15
MD0 to MD5
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
16
VSS
—
Ground terminal
17
MD6
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
18
VDD3
—
Power supply terminal (+3.3V)
19
MD7
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
20
VSS
—
Ground terminal
21
MD8
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC510)
22
VDD3
—
Power supply terminal (+3.3V)
23 to 28
MD9 to MD14
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC510)
29
MD15
I/O
Two-way data bus with the D-RAM (IC507)
30 to 36
NC
O
Not used (open)
37
MCE
O
Chip enable signal output to the program ROM (IC510)
38
MWE
O
Write enable signal output to the D-RAM (IC507)
39
VSS
—
Ground terminal
40
CAS
O
Column address strobe signal output to the D-RAM (IC507)
41
VDD3
—
Power supply terminal (+3.3V)
42
RAS0
O
Row address strobe signal output to the D-RAM (IC507)
43
RAS1
O
Row address strobe signal output terminal Not used (open)
44, 45
MA10, MA9
O
Address signal output to the program ROM (IC510)
46
MA8
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
47
VSS
—
Ground terminal
48
MA7
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
49
VDD3
—
Power supply terminal (+3.3V)
50 to 52
MA6 to MA4
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
53
VSS
—
Ground terminal
54
MA3
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
55
VDD3
—
Power supply terminal (+3.3V)
56 to 58
MA2 to MA0
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
59
PGIO7
I/O
Not used (open)
60
RESET
I
Reset signal input from the video CD controller (IC502) “L”: reset
61
VDDMAX-IN
I
Fix the maximum input voltage each input terminal and in/out terminal
62 to 64
NC
O
Not used (open)
65
AGND-DAC
—
Ground terminal (for D/A converter)
66
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
67
COMPOS OUT
O
Composite video signal output terminal Not used (open)
68
AGND-DAC
—
Ground terminal (for D/A converter)
69
Y-OUT
O
Luminance video signal output terminal
70
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
37
MCE-SV7
Pin No.
Pin Name
I/O
Description
71
AGND-DAC
—
Ground terminal (for D/A converter)
72
RREF
I
Fix the video signal output level control
73
VREF
O
Reference voltage (+1.235V) output terminal
74
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
75
C-OUT
O
Chrominance video signal output terminal
76
AGND-DAC
—
Ground terminal (for D/A converter)
77
CLK-SEL0
I
GCK (pin <z/b ) selection terminal “L”: external clock, “H”: internal clock (fixed at “H”)
78
CLK-SEL1
I
DA-XCLK (pin ih) selection (1) terminal Fixed at “H” in this set
79
CLK-SEL2
I
DA-XCLK (pin ih) selection (2) terminal Fixed at “H” in this set
80
VSS
—
Ground terminal
81
RESERVED
I
Selection the operation clock 42.336 MHz (fixed at “L”)
82
VDD3
—
Power supply terminal (+3.3V)
83
DA-EMP
O
Not used (open)
84
RESERVED
O
Not used (open)
85
AGND-PLL
—
Ground terminal (for PLL system)
86
DA-XCLK
I
Main reference clock signal (16.9344 MHz=384fs) input from the D/A converter (IC509)
87
AVDD-PLL
—
Power supply terminal (+3.3V) (for PLL system)
88 to 90 PGIO4 to PGIO6
I/O
Not used (open)
91
PGIO0
I/O
Not used (open)
92
PGIO8
I/O
Not used (open)
93
VSYNC
O
Vertical synchronized signal output to the video CD controller (IC502)
94
AVDD-PLL
—
Power supply terminal (+3.3V) (for PLL system)
95 to 97
NC
O
Not used (open)
98
AGND-PLL
—
Ground terminal (for PLL system)
99
VSS
—
Ground terminal
100
NC
O
Not used (open)
101
HSYNC
O
Horizontal synchronized signal output to the video CD controller (IC502)
102
VDD3
—
Power supply terminal (+3.3V)
103
VCK-OUT
O
Not used (open)
104
VSS
—
Ground terminal
105
GCK
I
Not used (open)
106
VCK-IN
I
Main clock for video signal processor input from the D/A converter (IC509) (27 MHz)
107
GCKOUT/DA-EMP
O
Not used (open)
108
DA-LRCK
O
Digital audio L/R sampling clock signal (44.1 kHz) output to the D/A converter (IC509)
109
VDDMAX-OUT
O
Fix the maximum output voltage (+5V) certain output terminal
110
DA-DATA
O
Digital audio data output to the D/A converter (IC509)
111
DA-BCK
O
Digital audio bit clock signal (2.8224 MHz) output to the D/A converter (IC509)
112
HD-OUT
O
Serial data output to the video CD controller (IC502)
113
HRDY
O
Ready signal output to the video CD controller (IC502)
114
HINT
O
Interrupt request signal output to the video CD controller (IC502)
115
CDG-SCK
I/O
Not used (open)
116
VSS
—
Ground terminal
117
HCK
I
Serial data transfer clock signal input from the video CD controller (IC502)
118
VDD3
—
Power supply terminal (+3.3V)
119
HD-IN
I
Serial data input from the CD mechanism controller (IC502)
120
VDD3
—
Power supply terminal (+3.3V)
38
MCE-SV7
Pin No.
Pin Name
I/O
Description
121
HSEL
I
Command selection signal input from the video CD controller (IC502)
122
CDG-SDATA
I
Not used (fixed at “L”)
123
CDG-VFSY
I
Not used (fixed at “L”)
124
CDG-S0S1
I
Not used (fixed at “L”)
125 to 128
NC
O
Not used (open)
39
MCE-SV7
•
MAIN BOARD IC401 M30620MAA-B53FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 7
—
—
Not used (open)
8
BYTE
I
External data bus line byte selection signal input “L”: 16 bits, “H”: 8 bits
Not used (fixed at “L”)
Not used (fixed at “L”)
9
CNVSS
—
To flash memory connector Not used (open)
10
—
—
Not used (fixed at “L”)
11
—
—
Not used (open)
12
RESET
I
Reset signal input from the tuner unit (ST-SV7)
13
X-OUT
O
System clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
X-IN
I
System clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+5V)
17
NMI
I
Non-maskable interrupt input terminal (fixed at “H” in this set)
18
—
—
Not used (open)
19
SCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used (open)
20 to 23
—
—
Not used (open)
24
BU PWM 3
O
RFDC PWM signal output terminal Not used (open)
25
—
—
Not used (open)
26
BU PWM 2
O
Tracking error PWM signal output terminal Not used (open)
27
—
—
Not used (open)
28
BU PWM 1
O
Focus error PWM signal output terminal Not used (open)
29
IIC-CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the video CD
controller and tuner unit (ST-SV7)
controller and tuner unit (ST-SV7)
30
IIC-DATA
I/O
Communication data bus with the video CD controller and tuner unit (ST-SV7)
31
—
—
Not used
32
SQ-DATA-IN
I
Subcode Q data input from terminal Not used (open)
33
SQ-CLK
O
Subcode Q data reading clock signal output terminal Not used (open)
34
RTS1
—
Not used
35
CD-DATA
O
CD decode data output terminal Not used (open)
36
SENS
I
Internal status (SENSE) signal input terminal Not used (open)
37
CD-CLK
O
Serial data transfer clock signal output terminal Not used (open)
38
CD POWER
O
Power on/off control signal output for the video and CD mechanism deck section
“L”: standby, “H”: power on
“L”: standby, “H”: power on
39
—
—
Not used (open)
40
HOLD
O
Automatic power control hold signal output terminal Not used (open)
41
—
—
Not used (fixed at “L”)
42
XLT
O
Serial data latch pulse output to terminal Not used (open)
43
XRST
O
Reset signal output terminal Not used (open)
44
LOAD-IN
O
Loading motor drive signal (load-in direction) output the motor driver (IC701)
45
LOAD-OUT
O
Loading motor drive signal (load-out direction) output the motor driver (IC701)
46
OPEN
I
Sub tray load in/out detect switch (S742) input “L”: sub tray is chucking position
47
CLOSE
I
Sub tray load in/out detect switch (S742) input “L”: sub tray slides out of chucking position
48
T-SENS1
I
Detection input from the disc tray 1 height sensor (IC731)
“H”: disc tray 1 position is chucking position
“H”: disc tray 1 position is chucking position
49
T-SENS2
I
Detection input from the disc tray 2 height sensor (IC732)
“H”: disc tray 2 position is chucking position
“H”: disc tray 2 position is chucking position
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