Sony MCE-SV7 / MHC-SV7AV Service Manual ▷ View online
29
MCE-SV7
• IC Block Diagrams
– BD Board –
– BD Board –
IC101
CXD3068Q
DOUT
LRCK
PCMD
BCK
DVDD2
ASYE
MD2
EMPH
XTSL
DVSS2
XTAI
XTAO
SQSO
SQCK
SCSY
SBSO
EXCK
SOUT
SOCK
XOLT
SE
TE
VC
TES1
TEST1
DVSS1
FRDR
FFDR
TRDR
TFDR
SRDR
SFDR
DVDD1
FSTO
SSTP
MDP
LOCK
PWMI
FOK
DFCT
DIGITAL
CLV
PROCESSOR
OSC
DIGITAL
OUT
EFM
DEMODULATOR
32K
RAM
ERROR
CORRECTOR
D/A DIGITAL
INTERFACE
MIRR, DFCT,
FOK
DETECTOR
CPU
INTERFACE
SUBCODE
PROCESSOR
SERVO
AUTO
SEQUENCER
SERVO INTERFACE
DVDD0
XRST
MUTE
D
ATA
XLA
T
CLOK
SENS
SCLK
A
TSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
WDCK
DVSS0
COUT
MIRR
A
VDD0
IGEN
A
VSS0
ADIO
RFDC
CE
TE
A
VSS1
RF
AC
ASYI
ASYO
BIAS
A
VDD1
PCO
FILI
FILO
CL
TV
V16M
VCTL
VPCO
59 58
57 56 55 54 53 52
51 50 49 48
47 46 45 44 43 42 41
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
OPERA
TIONAL
AMPLIFIER &
ANALOG SWITCH
A/D
CONVER
TER
FOCUS
PWM
GENERATOR
TRACKING
PWM
GENERATOR
SLED
PWM
PWM
GENERATOR
FOCUS
SERVO
SERVO
DSP
TRACKING
SERVO
DSP
SLED
SERVO
DSP
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
60
30
MCE-SV7
IC103
CXA2581N-T4
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
–
+
–
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
RW/ROM
VC
RW/ROM
DVC
+
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
–
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
O
UT2
O
UT1
RNF
VM
VCC
FIN
GND
RIN
– DRIVER Board –
IC701
BA6956AN
31
MCE-SV7
IC304
BA7665FS-E2
IC303
NJM2209M (TE2)
– VMP Board –
IC302
NJM2255M (TE2)
6
5
1
2
3
4
7
8
TINT
GND
BGP
V OUT
COLOR OFFSET
COLOR
V IN
V+
HUE ADJUST
–X
+Ø
SATURATION
ADJUST
(COLOR BURST)
SATURATION
ADJUST
(COLOR BURST)
1
2
3
4
5
6
7
14
VIDEO
OUTPUT
N.C
N.C
N.C
GND
N.C
V +
CONTROL
N.C
DIFFERENTIATION
INPUT
VIDEO
INPUT
PHASE
DELAY
DIFFERENTIATION
OUTPUT
13
12
11
10
9
8
FREQUENCY
CHARACTERISTIC
COMPENSATION
LPF
SWITCH
CONTROL
SECONDARY
DIFFERENTIATION
GAIN ADJ
LOWER
LIMITER
(1)
LOWER
LIMITER
(2)
CLAMP
(
SYNC
)
CHIP
1
15
16
2
3
4
5
6
7
8
9
6dB
75
Ω
6dB
75
Ω
6dB
75
Ω
20k
MUTEA
INA
GND
GND
GND
N.C.
INB
MUTEB
CHROMA MUTE
MUTE
VCC1
OUTA1
OUTA2
VCC2
MIXOUT1
MIXOUT2
N.C.
OUTB
14
13
12
11
10
IC509
PCM1727E-2/T2
1
2
3
4
5
6
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
POWER
SUPPLY
CLOCK MANAGER
•
DUAL PLL
AUDIO
DATA INPUT
INTERFACE
8 TIME OVER
SAMPLING DIGITAL
FILTER
•
FUNCTION
CONTROL
MODE
CONTROL
MULTI LEVEL
∆Σ
MODULATOR
MULTI LEVEL
∆Σ
MODULATOR
5 LEVEL
DAC
5 LEVEL
DAC
CR LPF
•
OUTPUT
AMP
CR LPF
•
OUTPUT
AMP
BPZ
CONTROL
13
OPEN
XT1
PGND
VCP
MCKO
RSV
SCKO3
ML
MC
MD
RSTB
VOUTR
AGND
VCA
ZERO
BCK
DATA
LRCK
SCKO2
SCKO1
VDD
DGND
XT2
384fs
15
14 VOUTL
CAP
32
MCE-SV7
6-17.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC101 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the video CD controller (IC502) “L”: reset
3
MUTING
I
Muting on/off control signal input from the video CD controller (IC502) “H”: muting on
4
DATA
I
Serial data input from the video CD controller (IC502)
5
XLAT
I
Serial data latch pulse signal input from the video CD controller (IC502)
6
CLOK
I
Serial data transfer clock signal input from the video CD controller (IC502)
7
SENS
O
Internal status (SENSE) signal output to the video CD controller (IC502)
8
SCLK
I
SENSE serial data reading clock signal input from the video CD controller (IC502)
9
ATSK
I/O
Input/output terminal for anti-shock Not used (pull down)
10
WFCK
O
Write frame clock signal output terminal Not used (open)
11
XUGF
O
RFCK signal output terminal Not used (open)
12
XPCK
O
XPCK signal output terminal Not used (open)
13
GFS
O
Guard frame sync signal output terminal Not used (open)
14
C2PO
O
C2 pointer signal output to the CL680T (IC505)
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the video CD controller (IC502)
16
C4M
O
4.2336 MHz clock signal output terminal Not used (open)
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output terminal Not used (open)
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output terminal Not used (open)
20
MIRR
O
Mirror signal output terminal Not used (open)
21
DFCT
I/O
Defect signal input/output terminal Not used (open)
22
FOK
O
Focus OK signal output terminal Not used (open)
23
PWMI
I
Spindle motor external control signal input terminal Not used (fixed at “L”)
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor (M3) servo drive signal output to the AN41020A (IC102)
26
SSTP
I
Detection signal input from limit in switch of the optical pick-up block
The optical pick-up is inner position when “H”
The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used (open)
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output to the AN41020A (IC102)
30
SRDR
O
Sled servo drive PWM signal (–) output to the AN41020A (IC102)
31
TFDR
O
Tracking servo drive PWM signal (+) output to the AN41020A (IC102)
32
TRDR
O
Tracking servo drive PWM signal (–) output to the AN41020A (IC102)
33
FFDR
O
Focus servo drive PWM signal (+) output to the AN41020A (IC102)
34
FRDR
O
Focus servo drive PWM signal (–) output to the AN41020A (IC102)
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test (fixed at “L”)
37
TES1
I
Input terminal for the test (fixed at “L”)
38
VC
I
Middle point voltage (+1.65V) input from the CXA2581N (IC103)
39
FE
I
Focus error signal input from the CXA2581N (IC103)
40
SE
I
Sled error signal input from the CXA2581N (IC103)
41
TE
I
Tracking error signal input from the CXA2581N (IC103)
42
CE
I
Middle point servo analog signal input from the CXA2581N (IC103)
43
RFDC
I
RF signal input from the CXA2581N (IC103)
44
ADIO
O
Output terminal for the test Not used (open)
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