Sony MCE-SV7 / MHC-SV7AV Service Manual ▷ View online
33
MCE-SV7
Pin No.
Pin Name
I/O
Description
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the CXA2581N (IC103)
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used (fixed at “H”)
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used (open)
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used (open)
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on
Not used (fixed at “H”)
Not used (fixed at “H”)
63
MD2
I
Digital out on/off control signal input from terminal Not used (fixed at “H”)
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
64
DOUT
O
Digital audio signal output to the OPTICAL OUT (IC102)
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CL680T (IC505)
66
PCMD
O
Serial data output to the CL680T (IC505)
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the CL680T (IC505)
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used (open)
“H” is output when playback disc is emphasis on Not used (open)
69
XTSL
I
System clock frequency setting signal input from the CL680T (IC505)
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “H” in this set)
“L”: 16.9344 MHz, “H”: 33.8688MHz (fixed at “H” in this set)
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.8688 MHz)
72
XTAO
O
System clock output terminal (33.8688 MHz) Not used (open)
73
SOUT
O
Serial data output terminal Not used (open)
74
SOCK
O
Serial data reading clock signal output terminal Not used (open)
75
XOLT
O
Serial data latch pulse signal output terminal Not used (open)
76
SQSO
O
Subcode Q data output to the video CD controller (IC502)
77
SQCK
I
Subcode Q data reading clock signal input from the video CD controller (IC502)
78
SCSY
I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used (fixed at “L”)
79
SBSO
O
Subcode serial data output terminal Not used (open)
80
EXCK
I
Subcode serial data reading clock signal input terminal Not used (open)
34
MCE-SV7
•
VMP BOARD IC502 M30622MGA-A59FP (VIDEO CD CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
SENSE
I
Internal status (SENSE) signal input from the CXD3068Q (IC101)
2
SENSE CLK
O
Sense serial data reading clock signal output to the CXD3068Q (IC101)
3
RESOLUTION
O
Serial data output to the Y amplifier (IC303)
4
CROMA LEVEL
O
Serial data latch pulse output to the C amplifier (IC302)
5
DSP CLK
O
Serial data transfer clock signal output to the CXD3068Q (IC101)
6
TSENS
I
Disc tray status detection signal input terminal Not used (open)
7
REMOTE IN
I
Remote control signal input terminal Not used (open)
8
BYTE
I
External data bus line byte selection signal input terminal
“L”: 16 bit, “H”: 8 bit (fixed at “L”)
“L”: 16 bit, “H”: 8 bit (fixed at “L”)
9
CNVSS
—
Ground terminal Not used
10
DSP MUTING
O
Muting on/off control signal output to the CXD3068Q (IC101) “H”: muting on
11
CTRL1
O
Clock selection signal output to the CXD3068Q (IC101)
“L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
“L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
12
XRESET
I
Reset signal input from the tuner unit (ST-SV7) “L”: reset
13
XOUT
O
Main system clock output terminal (10 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (10 MHz)
16
VCC
—
Power supply terminal (+5V)
17
NMI
I
Non-maskable interrupt input terminal (fixed at “H” in this set)
18
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
19
DSENS
I
Disc status detection signal input terminal Not used (open)
20
CL680 HINT
I
Interrupt request signal input from the CL680T (IC505)
21
H.SYNC IN
O
Horizontal synchronized signal input from the CL680T (IC505)
22
BGP
O
BGP signal output to the C amplifier (IC302)
23
—
—
Not used (open)
24
PWM3
O
RFDC PWM signal output to the CXA2581N (IC103)
25
—
—
Not used (open)
26
PWM2
O
PWM signal output to the CXA2581N (IC103)
27
—
—
Not used (open)
28
PWM1
O
Focus servo drive PWM signal output to the CXA2581N (IC103)
29
I2C.CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the system
controller (IC401) and tuner unit (ST-SV7)
controller (IC401) and tuner unit (ST-SV7)
30
I2C.DATA
I/O
Communication data bus with the system controller (IC401) and tuner unit (ST-SV7)
31
DATA1O
O
Serial data output terminal Not used
32
DATA1I
I
Serial data input terminal Not used
33
CLK1
O
Serial data transfer clock signal output terminal Not used
34
RTSI
I
Reset signal input terminal Not used
35
DATAO
O
Serial data output to the CL680T (IC505) and D/A converter (IC509)
36
DATAI
I
Serial data input from the CL680T (IC505)
37
CLKI
O
Serial data transfer clock signal output to the CL680T (IC505) and D/A converter (IC509)
38
P.ON
O
Power on/off control signal output terminal Not used (open)
39
BUS XRDY
I
Ready signal input terminal Not used (fixed at “H”)
40
BUS
O
Not used (open)
41
BUS XHOLD
I
Hold signal input terminal Not used (fixed at “H”)
42, 43
BUS
O
Not used (open)
44
OSD.LANGUAGE
I
Destination setting terminal “L”: chinese, “H”: others (fixed at “H” in this set)
45
VSYNC
I
Vertical synchronized signal input from theCL680T (IC505) “L” active
35
MCE-SV7
Pin No.
Pin Name
I/O
Description
46
BUS XWRL
O
Not used
47
LO.BOOST
O
Low boost control signal output terminal Not used (open)
48
AUDIO MUTING
O
Audio muting on/off control signal output terminal “L”: muting on Not used (open)
49
LOAD OUT
O
Loading motor drive signal output terminal Not used (open)
50
LOAD IN
O
Loading motor drive signal output terminal Not used (open)
51
INSW
I
Disc detection (load in) switch input terminal Not used (fixed at “H”)
52
OUTSW
I
Disc detection (load out) switch input terminal Not used (open)
53
MODEL1
I
Destination setting terminal (open)
54
MODEL2
I
Destination setting terminal (open)
55
TBLL
O
Table motor drive signal output terminal Not used (open)
56
TBLR
O
Table motor drive signal output terminal Not used (open)
57 to 59
ENC1 to ENC3
I
Disc tray address detection signal input terminal Not used (open)
60, 61
—
O
Not used (open)
62
VCC
—
Power supply terminal (+5V)
63
—
O
Not used (open)
64
VSS
—
Ground terminal
65
V.MUTE
O
Video muting on/off control signal output to the Y/C decoder “L”: muting on
66
DAC RESET
O
Reset signal output to the D/A converter (IC509)
67 to 72
A5 to A0
O
Address signal output for the external device Not used (open)
73
TEST LED
O
LED drive signal output for the self diagnosis indicator Normally: “L” (LED on)
74
TEST1
I
Setting terminal for the test mode 1 (for VCD check)
Normally: fixed at “H” (“L”: test mode)
Normally: fixed at “H” (“L”: test mode)
75
TEST2
I
Setting terminal for the test mode 2 (for SERVO check)
Normally: fixed at “H” (“L”: test mode)
Normally: fixed at “H” (“L”: test mode)
76
TEST3
I
Setting terminal for the test mode 3 Normally: fixed at “H” (“L”: test mode)
Not used (fixed at “H”)
Not used (fixed at “H”)
77
DEVICE RESET
O
System reset signal output to the CXD3068Q (IC101) and AN41020A (IC102) “L”: reset
78
STANDBY
O
Standby on/off control signal output terminal Not used (open)
79
FL CS
O
Chip select signal output terminal Not used (open)
80
OFF OUT
O
Blank control signal output terminal Not used (open)
81
LPH
O
Laser power control signal output terminal Not used (open)
82
LD ON
O
Laser on/off selection signal output to the CXA2561N (IC103) “H”: laser on
83
SUBQ CLK
O
Subcode Q data reading clock signal output to the CXD3068Q (IC101)
84
SUBQ DATA
I
Subcode Q data input from the CXD3068Q (IC101)
85
CL680 HRDY
I
Ready status detection signal input from the CL680T (IC505)
86
CL680 RESET
O
Reset signal output to the CL680T (IC505) “L”: reset
87
CL680 HSEL
O
Command selection signal output to the CL680T (IC505)
88
DF LATCH
O
Serial data latch pulse output to the D/A converter (IC509) “L” active
89
MIC CTRL
O
Mic control signal output terminal Not used (open)
90 to 92
KEY1 to KEY3
I
Key input terminal Not used (open)
93
NT/PAL
I
Video system (NTSC/PAL) select signal input terminal
94
MUSIC VOL
I
Volume input terminal Not used (fixed at “H”)
95
DSP DATA
O
Serial data output to the CXD3068Q (IC101)
96
AVSS
—
Ground terminal (for A/D conversion)
97
DSP LATCH
O
Serial data latch pulse output to the CXD3068Q (IC101)
98
VREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
99
AVCC
—
Power supply terminal (+5V) (for A/D conversion)
100
AMP.ON
O
Power amplifier on/off selection signal output terminal Not used (open)
36
MCE-SV7
•
VMP BOARD IC505 CL680T-D1 (MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used (open)
2
VSS
—
Ground terminal
3
CD-BCK
I
CD decode bit clock signal (2.8224 MHz) input from the CXD3068Q (IC101)
4
CD-DATA
I
CD decode data input from the CXD3068Q (IC101)
5
CD-LRCK
I
CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3068Q (IC101)
6
CD-C2PO
I
CD decode C2 error data input from the CXD3068Q (IC101)
7 to 9
NC
O
Not used (open)
10 to 15
MD0 to MD5
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
16
VSS
—
Ground terminal
17
MD6
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
18
VDD3
—
Power supply terminal (+3.3V)
19
MD7
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC510)
20
VSS
—
Ground terminal
21
MD8
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC510)
22
VDD3
—
Power supply terminal (+3.3V)
23 to 28
MD9 to MD14
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC510)
29
MD15
I/O
Two-way data bus with the D-RAM (IC507)
30 to 36
NC
O
Not used (open)
37
MCE
O
Chip enable signal output to the program ROM (IC510)
38
MWE
O
Write enable signal output to the D-RAM (IC507)
39
VSS
—
Ground terminal
40
CAS
O
Column address strobe signal output to the D-RAM (IC507)
41
VDD3
—
Power supply terminal (+3.3V)
42
RAS0
O
Row address strobe signal output to the D-RAM (IC507)
43
RAS1
O
Row address strobe signal output terminal Not used (open)
44, 45
MA10, MA9
O
Address signal output to the program ROM (IC510)
46
MA8
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
47
VSS
—
Ground terminal
48
MA7
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
49
VDD3
—
Power supply terminal (+3.3V)
50 to 52
MA6 to MA4
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
53
VSS
—
Ground terminal
54
MA3
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
55
VDD3
—
Power supply terminal (+3.3V)
56 to 58
MA2 to MA0
O
Address signal output to the D-RAM (IC507) and program ROM (IC510)
59
PGIO7
I/O
Not used (open)
60
RESET
I
Reset signal input from the video CD controller (IC502) “L”: reset
61
VDDMAX-IN
I
Fix the maximum input voltage each input terminal and in/out terminal
62 to 64
NC
O
Not used (open)
65
AGND-DAC
—
Ground terminal (for D/A converter)
66
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
67
COMPOS OUT
O
Composite video signal output terminal Not used (open)
68
AGND-DAC
—
Ground terminal (for D/A converter)
69
Y-OUT
O
Luminance video signal output terminal
70
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
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