Sony ICF-CD513 Service Manual ▷ View online
– 38 –
IC551
CXD2589Q
PWM
PWM
1
2 3
4 5 6
12
13
14
15 16 17
19 20
34
27
24
23
25
21
61
63
64
66
67
68
69
70
71
72
73
74
75
77
78
79
80
OSC
62
65
76
7 8 9
10
11
18
22
28
26
33
32
31
30
29
36
35
40
39
38
37
45
44
43
42
41
50
49
48
47
46
55
54 53 52 51
59 58 57
56
60
EFM
DEMODULATOR
ERROR
CORRECTOR
16k
RAM
D/A
INTERFACE
CLOCK
GENERATOR
SERVO
AUTO
SEQUENCER
CPU
INTERFACE
DIGITAL
OUT
SUB CODE
PROCESSOR
3rd-ORDER
NOISE SHAPER
OVER SAMPLING
DIGITAL FILTER
SERIAL-IN
INTERFACE
DIGITAL
CLV
OSC
DIGITAL
PLL
ASYMMETRY
CORRECTOR
LRCKI
LRCK
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
V16M
VCTL
VCTL
VCKI
VPCO1
TES1
TES0
PWMI
MDP
VDD
SYSM
AVSS
AVDD
XTAI
XVDD
AVSS
LOUT1
AIN1
AOUT1
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
XRST
XRST
VDD
VSS
EXCK
SBSO
SCOR
WFCK
ENPHI
EMPH
DOUT
C4M
XTSL
C2PO
GFS
XPCK
XUGF
VDD
VSS
BCKI
BCK
PCMDI
PCMD
VSS
LMUTE
RMUTE
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
XLON
FOK
VDD
VSS
– 39 –
IC591
BA6898FP
IC701
BA6208
+
–
LEVEL SHIFT
28
27
26
25
24
22
21
20
19
18
17
16
+
–
LEVEL SHIFT
+
–
VCC
VCC
+
–
–
LEVEL SHIFT
+
–
–
LEVEL SHIFT
1
2
3 4 5 6
7 8
9 10
11
12 13
14
REGULATOR
BIAS, T. S. D
BIAS, T. S. D
MONITOR
+
–
DRIVER
MUTE
+
–
15
23
NC
GND
OUT4-B
OUT4-A
IN4
IN4
,
VREF I
N
VCC
VCC
IN3
,
IN3
OUT3-A
OUT3-B
NC
OPIN-B
OPOUT
GND
OUT2-B
OUT2-A
IN2
IN2
,
GND
MUTE
REGOUT
REG-B
RESET
IN1
OUT1-B
OUT1-A
1
2
3
4
5
6
7
8
9
NC
OUTPUT 2
Vcc
GND
NC
INPUT 2
INPUT 1
NC
MOTOR
DRIVE
MOTOR
DRIVE
REG
SWITCH
SWITCH
OUTPUT1
– 40 –
6-9.
IC PIN FUCTION DESCRIPTION
•
MAIN BOARD IC401
µ
PD789406AGC-017-8BT (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VDD1
—
Power supply terminal (+5V)
2
BIAS
O
Bias output for the liquid crystal display drive
3 to 5
VLC0 to VLC2
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
6
VSS1
—
Ground terminal
7 to 10
COM0 to COM3
O
Common drive signal output to the liquid crystal display (LCD401)
11 to 26
SEG0 to SEG15
O
Segment drive signal output to the liquid crystal display (LCD401)
27 to 31
NC
—
Not used (fixed at “L”)
32
BUZ MUT
O
Buzzer sound muting on/off control signal output terminal “L”: muting on
Not used (pull down)
Not used (pull down)
33
C RST
O
System reset signal output to the CXA1992BR (IC501) and CXD2589Q (IC551) “L”: reset
34
KS4
O
Key strobe signal output to the key matrix Not used (pull down)
35 to 38
KS0 to KS3
O
Key strobe signal output to the key matrix
39
AVDD
—
Power supply terminal (+5V) (for analog system)
40
AVREF
—
Reference voltage (+5V) terminal (for A/D converter)
41
VERSION0
I
Destination setting terminal “L”: US, Canadian models, “H”: AEP model
42
VERSION1
I
Destination setting terminal Not used (fixed at “L” in this set)
43
CLOSE
I
Disc table close detection switch (S480) input terminal “H”: disc table is closed
44
OPEN
I
Disc table open detection switch (S481) input terminal “H”: disc table is opened
45
C SENS2
I
Internal status signal (sense signal) input from the CXA1992BR (IC501)
46
C SENS1
I
Internal status signal (sense signal) input from the CXD2589Q (IC551)
47
C SQSO
I
Subcode Q data (80 bit serial) input from the CXD2589Q (IC551)
48
AVSS
—
Ground terminal (for analog system)
49
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2589Q (IC551)
50
C MUT
O
Digital muting on/off control signal output to the CXD2589Q (IC551) “H”: muting on
51
C SQCK
O
Subcode Q data (80 bit serial) reading clock signal output to the CXD2589Q (IC551)
52
AC IN
I
Power failure detection input terminal “L”: power failure, “H”: power on
53
BUZZER
O
Buzzer sound drive signal output terminal
54
C CLK
O
Serial data transfer clock signal output to the CXD2589Q (IC551)
55
C LAT
O
Serial data latch pulse signal output to the CXD2589Q (IC551)
56
C DATA
O
Serial data output to the CXD2589Q (IC551)
57
M MUT
O
Muting on/off control signal output terminal “H”: muting on Not used (pull down)
58
AMUT
I/O
At initial mode: Setting terminal for the test mode (CD manual mode) “L” CD manual mode
At normal mode: Audio line muting on/off control signal output terminal “L”: muting on
At normal mode: Audio line muting on/off control signal output terminal “L”: muting on
59
CD ON
I/O
At initial mode: Setting terminal for the test mode (CD auto mode) “L”: CD auto mode
At normal mode: Power on/off control signal output for the CD +5V power supply
“L”: CD power on
At normal mode: Power on/off control signal output for the CD +5V power supply
“L”: CD power on
60
RADIO ON
O
Power on/off control signal output for the radio +5V power supply “L”: radio power on
61
R DATA
O
PLL serial data output to the FM/AM PLL (IC51)
62
R CLK
O
PLL serial data transfer clock signal output to the FM/AM PLL (IC51)
63
R LAT
O
PLL serial data latch pulse signal output to the FM/AM PLL (IC51)
64
POWER ON
O
Front side speaker on/off control signal output terminal “H”: speaker on
65
SHIFT0
O
Shift clock output of the main system clock (4.194 MHz) “H” active Not used (pull down)
66
SHIFT1
O
Shift clock output of the main system clock (4.194 MHz) “H” active Not used (pull down)
67
RESET
I
System reset signal input from the reset signal generator (IC402) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
68
X2
O
Main system clock output terminal (4.194 MHz)
69
X1
I
Main system clock input terminal (4.194 MHz)
– 41 –
Pin No.
Pin Name
I/O
Description
70
VSS0
—
Ground terminal
71
VDD0
—
Power supply terminal (+5V)
72
XT2
O
Sub system clock output terminal (32.768 kHz)
73
XT1
I
Sub system clock input terminal (32.768 kHz)
74
IC
—
Internal connection terminal (connected to ground)
75
TRAY OPEN
O
Motor drive signal output to the loading motor drive (IC701) “H” active *1
76
TRAY CLOSE
O
Motor drive signal output to the loading motor drive (IC701) “H” active *1
77 to 80
KR0 to KR4
I
Key return signal input from the key matrix
*1 Disc table open/close motor (M480) control
Stop
Table In
Table Out
Brake
TRAY OPEN (pin ug )
“L”
“L”
“H”
“H”
TRAY CLOSE (pin uh )
“L”
“H”
“L”
“H”
Terminal
Mode
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