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Model
ICD-UX200 ICD-UX200F ICD-UX300 ICD-UX300F ICD-UX400F
Pages
44
Size
1.39 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
icd-ux200-icd-ux200f-icd-ux300-icd-ux300f-icd-ux40.pdf
Date
PREV: Sony PCM-M10 / PCM-M10P Service Manual

Sony ICD-UX200 / ICD-UX200F / ICD-UX300 / ICD-UX300F / ICD-UX400F Service Manual ▷ View online

ICD-UX200/UX200F/UX300/UX300F/UX400F
25
IC9005  XC6221B312NR (MAIN Board (5/5))
1
CE
2
VSS
4 VIN
3 VOUT
ON/OFF
CONTROL
VOLTAGE
REFERENCE
CURRENT
LIMIT
CE
ERROR AMP
R DISCHG
R1
R2
EACH
CIRCUIT
CE
CE
IC9002  S-1132B24-M5T1S (MAIN Board (5/5))
1
VIN
3
ON/OFF
2
VSS
5 VOUT
4 NC
ON/OFF
CIRCUIT
REFERENCE
VOLTAGE
CIRCUIT
OVER
CURRENT
PROTECT
CIRCUIT
ICD-UX200/UX200F/UX300/UX300F/UX400F
26
•  IC Pin Function Description
MAIN BOARD  IC2000  AK4645EZ-L (STEREO CODEC, MIC/HP AMP)
Pin No.
Pin Name
I/O
Description
1
MPWR
O
Power supply pin for microphone
2
VCOM
O
Common voltage output    Bias voltage of ADC output and DAC output
3
AVSS
—
Analog ground pin
4
AVDD
—
Analog power supply pin
5
VCOC/RIN3
O
PLL loop fi lter signal output
6
I2C
I
Control mode select signal input    “H”: I2C bus
7
PDN
I
Power down mode signal input    “H”: Power up, “L”: Power down, reset
8
CSN/CAD0
I
Chip select signal input
9
CCLK/SCL
I
Control clock signal input
10
CDTI/SDA
I
Control data signal input
11
SDTI
I
Audio serial data signal input
12
SDTO
O
Audio serial data signal output
13
LRCK
I/O
In/out channel clock signal input/output
14
BICK
I/O
Audio serial clock signal input/output
15
DVDD
—
Digital power supply pin
16
TVDD
—
Digital in/out power supply pin
17
MCKI
I
External master clock signal input    Not used. (Connect to ground.)
18
MCKO
O
External master clock signal output    Not used. (Open)
19
HVSS
—
Headphone amplifi er ground pin
20
HVDD
—
Headphone amplifi er power supply pin
21
HPR
O
R-CH headphone amplifi er signal output
22
HPL
O
L-CH headphone amplifi er signal output
23
MUTE
O
Mute signal output
24
RIN4/IN4–
I
R-CH analog signal input 4
25
LIN4/IN4+
I
L-CH analog signal input 4
26
ROUT/LON
O
R-CH line output    Not used. (Open)
27
LOUT/LOP
O
L-CH line output    Not used. (Open)
28
MIN/LIN3
I
Monaural analog signal input    Not used. (Open)
29
RIN2/IN2–
I
R-CH analog signal input 2
30
LIN2/IN2+
I
L-CH analog signal input 2
31
LIN1/IN1–
I
L-CH analog signal input 1
32
RIN1/IN1+
I
R-CH analog signal input 1
ICD-UX200/UX200F/UX300/UX300F/UX400F
27
MAIN BOARD  IC8000  LC823403A-08A5-16-E (SYSTEM CONTROL, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
B2
TEST1
I
Test pin 1
A1
TEST2
I
Test pin 2
C2
TEST3
I
Test pin 3
B1
TEST4
I
Test pin 4
D2
TEST5
I
Test pin 5
C1
TEST6
I
Test pin 6
C3
TCK
I
JTAG test clock signal input
D3
RTCK
O
JTAG test returned clock signal output
D1
NTRST
I
JTAG test reset signal input
E2
EXA16(A15)
O
External memory address bit 16 signal output    NOR address line signal output
D4
TDI
I
JTAG test data signal input
E3
EXA15(A14)
O
External memory address bit 15 signal output    NOR address line signal output
E1
EXA14(A13)
O
External memory address bit 14 signal output    NOR address line signal output
F2
TMS
I
JTAG test mode select signal input
E4
EXA13(A12)
O
External memory address bit 13 signal output    NOR address line signal output
E5
EXA12(A11)
O
External memory address bit 12 signal output    NOR address line signal output
F3
TDO
O
JTAG test data signal output
F1
NRES
I
Reset signal input
G2
EXA11(A10)
O
External memory address bit 11 signal output    NOR address line signal output
F4
VDD1
—
Digital power supply pin (+1.0V)
F5
EXA10(A9)
O
External memory address bit 10 signal output    NOR address line signal output
G3
VSS
—
Digital ground pin
H2
EXA9(A8)
O
External memory address bit 9 signal output    NOR address line signal output
G1
VDD2
—
Digital power supply pin (+3.1V)
G4
EXA20(A19)
O
External memory address bit 20 signal output    NOR address line signal output
G5
NCS0
O
External memory chip select signal output 0    NOR chip select signal output
H3
EXA21(P2E)
O
External memory address bit 21 signal output    NOR address line signal output
H1
NCS1
O
External memory chip select signal output 1    Not used in this set. (Open)
J2
NWRENWRL/NWE
O
External memory write/external memory write low byte signal output
H4
NCS2(P20)
O
External memory chip select 2 signal output    LCD chip select signal output
J1
NCS3(P10)
O
External memory chip select 3 signal output    RTC chip select signal output
H5
NRESET
I
Flash reset signal input
K2
NLBEXA0
O
External memory address bit 0/external memory low byte select signal output
Not used in this set. (Open) 
K1
NHBNWRH
O
External memory write/external memory write high byte signal output
Not used in this set. (Open)
J3
PHI(P11)
O
AHB bus clock signal output (32.768kHz)    FM DX/Local change signal output
J4
EXA19(A18)
O
External memory address bit 19 signal output    NOR address line signal output
K3
EXA18(A17)
O
External memory address bit 18 signal output    NOR address line signal output
L2
EXTFIQ(P2F)
I
External FIQ interruption signal input
L1
SCK0
O
Serial interface 0 clock signal output    RTC/LCD clock signal output
K4
EXA8(A7)
O
External memory address bit 8 signal output    NOR address line signal output
J5
EXA7(A6)
O
External memory address bit 7 signal output    NOR address line signal output
M1
SDO0
O
Serial interface 0 data signal output    RTC/LCD data signal output
M2
EXA6(A5)
O
External memory address bit 6 signal output    NOR address line signal output
L3
SDI0
I
Serial interface 0 data signal input    RTC data signal input    Not used in this set. 
L4
VDD1
—
Digital power supply pin (+1.0V)
K5
EXA5(A4)
O
External memory address bit 5 signal output    NOR address line signal output
M3
VSS
—
Digital ground pin
N1
EXA4(A3)
O
External memory address bit 4 signal output    NOR address line signal output
N2
VDD2
—
Digital power supply pin (+3.1V)
P1
EXA3(A2)
O
External memory address bit 3 signal output    NOR address line signal output
N3
EXA2(A1)
O
External memory address bit 2 signal output    NOR address line signal output
ICD-UX200/UX200F/UX300/UX300F/UX400F
28
Pin No.
Pin Name
I/O
Description
P2
SCK1(P14)
O
Serial interface 1 clock signal output    ADDA serial clock signal output
M4
SDO1(P15)
O
Serial interface 1 data signal output    ADDA serial data signal output
L5
SDI1(P16)
I
Serial interface 1 data signal input    ADDA serial data signal input
R1
TXD1(P2A)
O
UART1 transmission signal output    SP/HP change signal output
T1
RXD1(P2B)
O
UART1 reception signal output    SP shut down signal output
T2
TCLKA(P17)
O
Multiple timer external clock A signal output    CPU core voltage change signal output
R3
TCLKB(P18)
O
Multiple timer external clock B signal output    Battery level measure signal output
T3
TIOCA0(P19)
I/O
Multiple timer input capture/output compare A0 signal input/output    
Battery detect signal output
R4
VDD1
—
Digital power supply pin (+1.0V)
R2
TIOCB0(P1A)
I/O
Multiple timer input capture/output compare B0 signal input/output    
DAMP output on/off select signal output
P3
TIOCA1(P1B)
I/O
Multiple timer input capture/output compare A1 signal input/output    
OP LED (red) signal output
P4
TIOCB1(P1C)
I/O
Multiple timer input capture/output compare B1 signal input/output    
OP LED (green) signal output
R5
TXDO(P1D)
O
UART transmission signal output
T4
RXDO(P1E)
I
UART reception signal output
N4
PO0
I/O
Port pin 0 bit0    CPU power on signal output
P5
PO1
I/O
Port pin 0 bit1    Not used in this set. (Open)
R6
PO2
I/O
Port pin 0 bit2    AUDIO power on signal output
T5
PO3
I/O
Port pin 0 bit3    FM power on signal output
N5
PO4
I/O
Port pin 0 bit4    Charge on signal output
M5
PO5
I/O
Port pin 0 bit5    Charge measurement signal output
M6
XFCE2(P06)
O
Nand fl ash chip enable 2 signal output    LCD reset signal output
T6
XFCE3(P07)
O
Nand fl ash chip enable 3 signal output    Mute signal output
P6
VDD1
—
Digital power supply pin (+1.0V)
N6
VSS
—
Digital ground pin
R7
VDD2
—
Digital power supply pin (+3.1V)
M7
XFWE
O
Nand fl ash write enable signal output    Not used in this set. (Open)
N7
XFRE
O
Nand fl ash read enable signal output    Not used in this set. (Open)
T7
XALE
O
Nand fl ash address latch enable signal output     Not used in this set. (Open)
P7
XCLE
O
Nand fl ash command latch enable signal output    Not used in this set. (Open)
T8
XFCE1(P1F)
O
Nand fl ash chip enable 1 signal output    Not used in this set. (Open)
R8
XFCE0
O
Nand fl ash chip enable 0 signal output    Not used in this set. (Open)
M8
XFWP
O
Nand fl ash write protect signal output    Not used in this set. (Open)
N8
XFBSY
I
Nand fl ash busy signal input    Connected to ground in this set.
P8
FD0
I/O
Nand fl ash data bit 0 signal input/output
R9
FD1
I/O
Nand fl ash data bit 1 signal input/output
T9
FD2
I/O
Nand fl ash data bit 2 signal input/output
P9
FD3
I/O
Nand fl ash data bit 3 signal input/output
N9
FD4
I/O
Nand fl ash data bit 4 signal input/output
M9
FD5
I/O
Nand fl ash data bit 5 signal input/output
T10
FD6
I/O
Nand fl ash data bit 6 signal input/output
R10
FD7
I/O
Nand fl ash data bit 7 signal input/output
P10
VDD1
—
Digital power supply pin (+1.0V)
N10
VSS
—
Digital ground pin
M10
VDD2
—
Digital power supply pin (+3.1V)
N11
SDWP
I
SD card write protect signal input    Connected to ground in this set.
T11
SDCD
I
SD card detect signal input    Connected to ground in this set.
R11
SDCMD
I/O
SD card command signal input/output
P11
SDCLK
O
SD card clock signal output
M11
SDAT1
I/O
SD card data bit 0 signal input/output
T12
SDAT2
I/O
SD card data bit 1 signal input/output 
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