Sony HT-XT3 Service Manual ▷ View online
HT-XT3
69
Pin No.
Pin Name
I/O
Description
K3
CAS
I
Command Input: CAS (along with CS) defi ne the command being entered.
K4
NO_USE
-
Not used
K5
NO_USE
-
Not used
K6
NO_USE
-
Not used
K7
CK
I
Clock: CK is differential clock input. All address and control input signals are sampled on the
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.
K8
VDD
-
Power Supply: 1.5V +/-0.075
K9
CKE
I
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signal and de-
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE
is asynchronous for self refresh exit. After V
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE
is asynchronous for self refresh exit. After V
REFCA
has become stable during the power on and
initialization sequence, it must be maintained during all operations (including Self-Refresh).
CKE must be maintained high throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
CKE must be maintained high throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
L1
NC
-
No Connect: No internal electrical connection is present.
L2
CS
I
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on system with multiple Ranks. CS is considered part of the command code.
Rank selection on system with multiple Ranks. CS is considered part of the command code.
L3
WE
I
Command Input: WE (along with CS) defi ne the command being entered.
L4
NO_USE
-
Not used
L5
NO_USE
-
Not used
L6
NO_USE
-
Not used
L7
A10
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
precharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank adresses.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
precharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank adresses.
L8
ZQ
-
Reference Pin for ZQ calibration
L9
NC
-
No Connect: No internal electrical connection is present.
M1
VSS
-
Ground
M2
BA0
I
Bank Address Inputs: BA0 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
M3
BA2
I
Bank Address Inputs: BA2 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
M4
NO_USE
-
Not used
M5
NO_USE
-
Not used
M6
NO_USE
-
Not used
M7
NC
-
No Connect: No internal electrical connection is present.
M8
VREFCA
-
Reference voltage for CA
M9
VSS
-
Ground
N1
VDD
-
Power Supply: 1.5V +/-0.075
N2
A3
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
N3
A0
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
N4
NO_USE
-
Not used
N5
NO_USE
-
Not used
N6
NO_USE
-
Not used
N7
A12
I
Address inputs: Provided the row address for active commands and the column address
for Read/Write commands to select one location out of the memory array in the respective
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).
for Read/Write commands to select one location out of the memory array in the respective
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).
HT-XT3
70
Pin No.
Pin Name
I/O
Description
N8
BA1
I
Bank Address Inputs: BA1 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
N9
VDD
-
Power Supply: 1.5V +/-0.075
P1
VSS
-
Ground
P2
A5
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P3
A2
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P4
NO_USE
-
Not used
P5
NO_USE
-
Not used
P6
NO_USE
-
Not used
P7
A1
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P8
A4
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P9
VSS
-
Ground
R1
VDD
-
Power Supply: 1.5V +/-0.075
R2
A7
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R3
A9
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R4
NO_USE
-
Not used
R5
NO_USE
-
Not used
R6
NO_USE
-
Not used
R7
A11
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R8
A6
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R9
VDD
-
Power Supply: 1.5V +/-0.075
T1
VSS
-
Ground
T2
RESET
I
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail
signal with DC high and low at 80% and 20% of V
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail
signal with DC high and low at 80% and 20% of V
DD
, example, 1.20V for DC high and 0.30V
for DC low.
T3
A13
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
T4
NO_USE
-
Not used
T5
NO_USE
-
Not used
T6
NO_USE
-
Not used
T7
NC
-
No Connect: No internal electrical connection is present.
T8
A8
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
T9
VSS
-
Ground
HT-XT3
71
MB-1408 BOAR
D (6/11) I
C3004 MB9BF128SPMC-GE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VCC
-
Power supply terminal (+3.3V)
2
NO USE
-
Not used
3
NO USE
-
Not used
4
NO USE
-
Not used
5
O-LED_DC
O
O-LED Data/command selection
6
TS_SDA
I/O
Touch Sensor Data
7
TS_SCL
I/O
Touch Sensor Clock
8
TS_INT
I
Touch Sensor Detect
9
TS_RST
O
Touch Sensor Reset
10
NO USE
-
Not used
11
PCONT_O-LED
O
Power Control for O-LED
12
O-LED_CS
O
O-LED Chip selection
13
O-LED_RESET
O
O-LED Reset operation
14
O-LED_DOUT
O
O-LED Driver Data OUT
15
O-LED_CLK
O
O-LED Driver Clock OUT
16
BD_SDO (IF_SDI)
I
BD --> IF-con Data IN
17
BD_SDI (IF_SDO)
O
IF-con --> BD Data OUT
18
BD_CLK
I
IF-con <-- BD Clock OUT
19
BD_CS
O
BD Chip Select
20
HDMI(9678)_SDA
I/O
Two-way I2C data bus with the HDMI transceiver
21
HDMI(9678)_SCL
I/O
I2C clock signal output to the HDMI transceiver
22
HDMI(9678)_RESET
O
Reset signal to the HDMI transceiver “H”: reset
23
HDMI(9678)_INT
I
Interrupt signal input from the HDMI transceiver
24
SIRCS_IN
I
SIRCS signal input from the remote control receiver
25
VSS
-
Ground terminal
26
NO USE
-
Not used
27
NO USE
-
Not used
28
NO USE
-
Not used
29
NO USE
-
Not used
30
NO USE
-
Not used
31
NO USE
-
Not used
32
NO USE
-
Not used
33
BD_LED
O
LED drive signal output terminal for the illumination (blue) “H”: LED on
34
NO USE
-
Not used
35
NFC_IRQ
I
Radio data reception signal input from the NFC module
36
VSS
-
Ground terminal
37
VCC
-
Power supply terminal (+3.3V)
38
NFC_RFDET
I
Magnetic fi eld detection signal input from the NFC module “L”: magnetic fi eld is detected
39
NFC_DATA
I/O
Bidirectional Pin that is used to send and receive memory addresses or data.
40
NFC_CLK
I/O
Clock input pin for data I/O timing
41
NO USE
-
Not used
42
NO USE
-
Not used
43
NO USE
-
Not used
44
C
I
Regulator stabilization capacity connecting pin
45
VSS
-
Ground terminal
46
VCC
-
Power supply terminal (+3.3V)
47
NO USE
-
Not used
48
DAMP_XPDN
O
DAMP Processor Power Down Control
49
INITX(RESET)
I
Micom reset port
50
DC_DET
I
Speaker DC detection signal input terminal “L”: speaker DC is detected
51
NO USE
-
Not used
52
NO USE
-
Not used
53
DAMP_ XRST
O
DAMP Processor Reset
54
DAMP_SCL
I/O
Serial data transfer clock signal output to the stream processor
55
DAMP_SDA
I/O
Two-way data bus with the stream processor
HT-XT3
72
Pin No.
Pin Name
I/O
Description
56
DAMP_ XMUTE
O
DAMP processor soft muting
57
NO USE
-
Not used
58
HDMI_IN1_INT
I
Interrupt signal input from the HDMI transceiver
59
HDMI_IN1_RESET
O
Reset signal output to the HDMI transceiver “H”: reset
60
NO USE
-
Not used
61
NO USE
-
Not used
62
CLIP
I
For Digital VACS (LOW: Detect Overfl ow)
63
5VPWR
O
Control for HDMI out 5V power
64
NO USE
-
Not used
65
SPARTA_PCONT
O
Power control for HDMI transceiver
66
NO USE
-
Not used
67
RG_PCONT
-
Rogue IC power control
68
MD1
I
UCOM Mode setting terminal
69
MD0
I
UCOM Mode setting terminal
70
X0
I
Clock signal output (4MHz)
71
X1
O
Clock signal output (4MHz)
72
VSS
-
Ground terminal
73
VCC
-
Power supply terminal (+3.3V)
74
NO USE
-
Not used
75
PCONT_AMP
O
DRIVER GVDD12V FET SW control
76
NO USE
-
Not used
77
NO USE
-
Not used
78
Update UART Rx
O
Special Update data serial
79
Update UART Tx
O
Special Update data serial
80
PCON_WOL_STDBY
O
Power control for WOL Standby mode
81
NO USE
-
Not used
82
NO USE
-
Not used
83
NO USE
-
Not used
84
NO USE
-
Not used
85
NO USE
-
Not used
86
NO USE
-
Not used
87
NO USE
-
Not used
88
NO USE
-
Not used
89
NO USE
-
Not used
90
AVCC
-
Power supply terminal (+3.3V)
91
AVSS
-
Ground terminal
92
AVRL
I
A/D converter analog reference voltage input pin
93
AVRH
I
Standard power supply pin for A/D converter
94
NO USE
-
Not used
95
NO USE
-
Not used
96
DRIVER_SD/
POWER_DET
I
DAMP Driver Shut Down and Pvdd Detect for Protect
97
HDMI(9575+9679)_
SCL
I/O
I2C clock signal output to the HDMI transceiver
98
HDMI(9575+9679)_
SDA
I/O
Two-way I2C data bus with the HDMI transceiver
99
HDMI(9575) INT
I
Interrupt signal input from the HDMI transceiver
100
OnChipDebug/CLK1
I
On Chip Debuger
101
(PROG_VUTX)
O
Programming UART TX (micom)
102
(PROG_VURX)
I
Programming UART RX (micom)
103
AC_CUT
I
AC cut detection signal input terminal “L”: AC cut is detected
104
HDMI (9575) RESET
O
Reset signal output to the HDMI transceiver “H”: reset
105
WOL_WLAN
I
WOL wake up detect port
106
NO USE
-
Not used
107
VCC
-
Power supply terminal (+3.3V)
108
VSS
-
Ground terminal
109
VCC
-
Power supply terminal (+3.3V)
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