Sony HT-XT3 Service Manual ▷ View online
HT-XT3
65
Pin No.
Pin Name
I/O
Description
AE23
NFD0
I/O
Two-way data bus with the NAND fl ash
AE24
NFWEN
O
Write enable signal output to the NAND fl ash
AE25
HTPLG_RX
O
Hot plug detection signal output to the HDMI IN 1 connector
AE26
PWR5V_RX2
I
Power supply voltage (+5V) input from the HDMI IN 2 connector
AF1, AF2
TP_MEMPLL,
TN_MEMPLL
-
Not used
AF3
NC
-
Not used
AF4
RDQ25
I/O
Two-way data bus with the SD-RAM
AF5
DGND12_K
-
Ground terminal
AF6
RDQ28
I/O
Two-way data bus with the SD-RAM
AF7
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF8, AF9
RDQ20, RDQ22
I/O
Two-way data bus with the SD-RAM
AF10
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF11, AF12
RA9, RA5
O
Address signal output to the SD-RAM
AF13
RCS_
O
Chip select signal output to the SD-RAM
AF14 to
AF16
RDQ3, RDQ1, RDQ9
I/O
Two-way data bus with the SD-RAM
AF17, AF18
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF20
RDQ5
I/O
Two-way data bus with the SD-RAM
AF21
NFD6
I/O
Two-way data bus with the NAND fl ash
AF22
NFCEN
O
Chip enable signal output to the NAND fl ash
AF23
NFD1
I/O
Two-way data bus with the NAND fl ash
AF24
NFALE
O
Address latch enable signal output to the NAND fl ash
AF25
UARXD
-
Not used
AF26
RESET_
I
Reset signal input from the system controller “L”: reset
AF27
DDC_SDA_RX
I/O
Two-way I2C data bus with the HDMI IN 1 connector
AF28
DDC_SCL_RX
O
I2C clock signal output to the HDMI IN 1 connector
AG1 to AG4
RDQ17, RDQ16,
RDQ26, RDQ27
I/O
Two-way data bus with the SD-RAM
AG5
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG6
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG7
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG8
RDQ21
I/O
Two-way data bus with the SD-RAM
AG10
RBA2
O
Bank address signal output to the SD-RAM
AG11,
AG13
RA2, RA11
O
Address signal output to the SD-RAM
AG14
RDQ0
I/O
Two-way data bus with the SD-RAM
AG16
RDQS0
O
Data strobe signal (positive) output to the SD-RAM
AG17
RCLK0
O
Clock signal (positive) output to the SD-RAM
AG18
RDQS1_
O
Data strobe signal (negative) output to the SD-RAM
AG19,
AG20
RDQ7, RDQ4
I/O
Two-way data bus with the SD-RAM
AG21 to
AG23
NFD7, NFD4, NFD2
I/O
Two-way data bus with the NAND fl ash
AG25
GPIO8
O
VBUS on/off control signal output terminal for WLAN/BT COMBO card “H”: VBUS on
AG26
VCLK
O
Serial data transfer clock signal output to the system controller
AG27
VDATA
I
Serial data input from the system controller
AG28
LCDRD
O
Serial data output to the system controller
AH1 to AH3
RDQ18, RDQ19,
RDQ24
I/O
Two-way data bus with the SD-RAM
AH4
RDQM3
O
Data mask signal output to the SD-RAM
AH5
RDQS2_
O
Data strobe signal (negative) output to the SD-RAM
AH6
RCLK1_
O
Clock signal (negative) output to the SD-RAM
AH7
RDQS3
O
Data strobe signal (positive) output to the SD-RAM
AH8
RDQ23
I/O
Two-way data bus with the SD-RAM
AH10,
AH11
RA0, RA7
O
Address signal output to the SD-RAM
AH13
RCKE
O
Clock enable signal output to the SD-RAM
HT-XT3
66
Pin No.
Pin Name
I/O
Description
AH14
RDQ2
I/O
Two-way data bus with the SD-RAM
AH16
RDQS0_
O
Data strobe signal (negative) output to the SD-RAM
AH17
RCLK0_
O
Clock signal (negative) output to the SD-RAM
AH18
RDQS1
O
Data strobe signal (positive) output to the SD-RAM
AH19
RDQM0
O
Data mask signal output to the SD-RAM
AH20
RDQ6
I/O
Two-way data bus with the SD-RAM
AH22,
AH23
NFD5, NFD3
I/O
Two-way data bus with the NAND fl ash
AH25
OPWRSB
O
Power control signal output to the system controller
AH26
UATXD
-
Not used
AH27
VSTB
-
Not used
AH28
IR
-
Not used
HT-XT3
67
MB-1408 BOARD
(1/11)
IC102, IC103 K4B2G1646Q-BCMA (SD-RAM)
Pin No.
Pin Name
I/O
Description
A1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A2
DQU5
I/O
Data Input/output: Bi-directional data bus.
A3
DQU7
I/O
Data Input/output: Bi-directional data bus.
A4
NO_USE
-
Not used
A5
NO_USE
-
Not used
A6
NO_USE
-
Not used
A7
DQU4
I/O
Data Input/output: Bi-directional data bus.
A8
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A9
VSS
-
Ground
B1
VSSQ
-
DQ Ground
B2
VDD
-
Power Supply: 1.5V +/-0.075
B3
VSS
-
Ground
B4
NO_USE
-
Not used
B5
NO_USE
-
Not used
B6
NO_USE
-
Not used
B7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
B8
DQU6
I/O
Data Input/output: Bi-directional data bus.
B9
VSSQ
-
DQ Ground
C1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
C2
DQU3
I/O
Data Input/output: Bi-directional data bus.
C3
DQU1
I/O
Data Input/output: Bi-directional data bus.
C4
NO_USE
-
Not used
C5
NO_USE
-
Not used
C6
NO_USE
-
Not used
C7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
C8
DQU2
I/O
Data Input/output: Bi-directional data bus.
C9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D1
VSSQ
-
DQ Ground
D2
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D3
DMU
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
D4
NO_USE
-
Not used
D5
NO_USE
-
Not used
D6
NO_USE
-
Not used
D7
DQU0
I/O
Data Input/output: Bi-directional data bus.
D8
VSSQ
-
DQ Ground
D9
VDD
-
Power Supply: 1.5V +/-0.075
E1
VSS
-
Ground
E2
VSSQ
-
DQ Ground
E3
DQL0
I/O
Data Input/output: Bi-directional data bus.
E4
NO_USE
-
Not used
E5
NO_USE
-
Not used
E6
NO_USE
-
Not used
HT-XT3
68
Pin No.
Pin Name
I/O
Description
E7
DML
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
E8
VSSQ
-
DQ Ground
E9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
F1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
F2
DQL2
I/O
Data Input/output: Bi-directional data bus.
F3
DQSL
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
F4
NO_USE
-
Not used
F5
NO_USE
-
Not used
F6
NO_USE
-
Not used
F7
DQL1
I/O
Data Input/output: Bi-directional data bus.
F8
DQL3
I/O
Data Input/output: Bi-directional data bus.
F9
VSSQ
-
DQ Ground
G1
VSSQ
-
DQ Ground
G2
DQL6
I/O
Data Input/output: Bi-directional data bus.
G3
DQSL
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
G4
NO_USE
-
Not used
G5
NO_USE
-
Not used
G6
NO_USE
-
Not used
G7
VDD
-
Power Supply: 1.5V +/-0.075
G8
VSS
-
Ground
G9
VSSQ
-
DQ Ground
H1
VREFDQ
-
Reference voltage for DQ
H2
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
H3
DQL4
I/O
Data Input/output: Bi-directional data bus.
H4
NO_USE
-
Not used
H5
NO_USE
-
Not used
H6
NO_USE
-
Not used
H7
DQL7
I/O
Data Input/output: Bi-directional data bus.
H8
DQL5
I/O
Data Input/output: Bi-directional data bus.
H9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
J1
NC
-
No Connect: No internal electrical connection is present.
J2
VSS
-
Ground
J3
RAS
I
Command Input: RAS (along with CS) defi ne the command being entered.
J4
NO_USE
-
Not used
J5
NO_USE
-
Not used
J6
NO_USE
-
Not used
J7
CK
I
Clock: CK is differential clock input. All address and control input signals are sampled on the
crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.
crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.
J8
VSS
-
Ground
J9
NC
-
No Connect: No internal electrical connection is present.
K1
ODT
I
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
K2
VDD
-
Power Supply: 1.5V +/-0.075
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