Sony HT-XT1 Service Manual ▷ View online
HT-XT1
53
Pin No.
Pin Name
I/O
Description
57
CBUS_HPD1
O
Hot plug detection control signal output to the HDMI IN 1 connector
58
R1PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 1 connector
59
DSDA2
I/O
Two-way I2C serial data bus with the HDMI IN 2 connector
60
DSCL2
I
I2C serial data transfer clock signal input from the HDMI IN 2 connector
61
CBUS_HPD2
O
Hot plug detection control signal output to the HDMI IN 2 connector
62
R2PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 2 connector
63
DSDA3
I/O
Two-way I2C serial data bus with the HDMI IN 3 connector
64
DSCL3
I
I2C serial data transfer clock signal input from the HDMI IN 3 connector
65
CBUS_HPD3
O
Hot plug detection control signal output to the HDMI IN 3 connector
66
R3PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 3 connector
67
TXDSDA
I/O
Two-way I2C serial data bus with the TV (ARC) HDMI OUT connector
68
TXDSCL
O
I2C serial data transfer clock signal output to the TV (ARC) HDMI OUT connector
69
TX_HPD
I
Hot plug detection signal input from the TV (ARC) HDMI OUT connector
70
MHL_CD0_GPIO0
-
Not used
71
APLL10
-
Power supply terminal (+1V)
72
XTALVCC33
-
Power supply terminal (+3.3V)
73
XTALOUT
O
System clock signal output terminal (27 MHz)
74
XTALIN
I
System clock signal input terminal (27 MHz)
75
XTALGND
-
Ground terminal
76
TPVDD10
-
Power supply terminal (+1V)
77
TXC–
O
TMDS clock (negative) signal output to the TV (ARC) HDMI OUT connector
78
TXC+
O
TMDS clock (positive) signal output to the TV (ARC) HDMI OUT connector
79
TX0–
O
TMDS data (negative) output to the TV (ARC) HDMI OUT connector
80
TX0+
O
TMDS data (positive) output to the TV (ARC) HDMI OUT connector
81
TDVDD10
-
Power supply terminal (+1V)
82
TX1–
O
TMDS data (negative) output to the TV (ARC) HDMI OUT connector
83
TX1+
O
TMDS data (positive) output to the TV (ARC) HDMI OUT connector
84
TX2–
O
TMDS data (negative) output to the TV (ARC) HDMI OUT connector
85
TX2+
O
TMDS data (positive) output to the TV (ARC) HDMI OUT connector
86
CVDD10
-
Power supply terminal (+1V)
87
ARCRX_TX
I
Digital audio signal input from the TV (ARC) HDMI OUT connector
88
WS0_OUT
O
L/R sampling clock signal output to the digital audio interface receiver
89
SCK0
O
Bit clock signal output to the digital audio interface receiver
90
SD0_0
O
Digital audio signal output to the digital audio interface receiver
91
MCLK
O
Master clock signal output to the digital audio interface receiver
92 to 94
SD0_1 to SD0_3
O
Digital audio signal output to the digital audio interface receiver
95
MUTEOUT
O
HDMI muting on/off control signal output terminal “H”: muting on
96
SPDIFOUT
O
S/PDIF audio signal output to the digital audio interface receiver
97
IOVCC33
-
Power supply terminal (+3.3V)
98
SDO_GPIO10
-
Not used
99
SDI_GPIO11
-
Not used
100
SS_GPIO8
-
Not used
HT-XT1
54
Pin No.
Pin Name
I/O
Description
1
SIRCS_IN
I
SIRCS signal input from the remote control receiver
2
N.A
O
Not used
3
DSP MOSI
O
Serial data output to the serial fl ash and DSP
4
DSP MISO
I
Serial data input from the serial fl ash and DSP
5
DSP_SPICLK
O
Serial data transfer clock signal output to the serial fl ash and DSP
6
BYTE
I
External data bus width selection signal input terminal Fixed at “L” in this unit
7
CNVss
I
Processor mode selection signal input terminal
8
ROM_SDA
I/O
Two-way data bus with the EEPROM
9
ROM_SCLK
O
Serial data transfer clock signal output to the EEPROM
10
RESET
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
11
Xout
O
System clock output terminal (8 MHz)
12
Vss
-
Ground terminal
13
Xin
I
System clock input terminal (8 MHz)
14
Vcc1
-
Power supply terminal (+3.3V)
15
CEC_I/O
I/O
Two-way CEC serial data with the HDMI connector
16
DIR_ZERO
I
Zero data detection signal input from the digital audio interface receiver
17
RFDET_NFC
I
Magnetic fi eld detection signal input from the NFC module “L”: magnetic fi eld is detected
18
DRIVE_OCP (DIAG)
I
Shut down signal input from the digital power amplifi er “L”: shut down
19
WL_DET
O
Not used
20
BT_LED
O
LED drive signal output terminal for the illumination (blue) “H”: LED on
21
WL_RST
O
Not used
22
N.A
O
Not used
23
HDMI_TX_5VPWR
O
+5V power on/off control signal output terminal for the TV (ARC) HDMI OUT connector
“H”: power on
“H”: power on
24
HDMI_NON_LPCM
O
Audio setting signal output terminal “L”: LPCM audio, “H”: HBR audio
25
DIR_ERROR
I
Error detection signal input from the digital audio interface receiver “L”: error
26
PCONT_DRV
O
Power on/off control signal output terminal for the digital power amplifi er “H”: power on
27
DAMP_SCL
O
Serial data transfer clock signal output to the stream processor
28
DAMP_SDA
I/O
Two-way data bus with the stream processor
29
M_TX_OUT
O
Serial data output to the DSP
30
M_RX_IN
I
Serial data input from the DSP
31
SCD/CLK1
I
Serial data transfer clock signal input terminal for fl ash writing
32
RTS1/MC_BT_CTS0
I
Clear to send signal input from the Bluetooth module
33
MC_BT_TXD0
O
Serial data output to the Bluetooth module
34
MC_BT_RXD0
I
Serial data input from the Bluetooth module
35
N.A
O
Not used
36
MC_BT_RTS
O
Return to send signal output to the Bluetooth module
37
P_CONT2
O
Power on/off control signal output terminal “H”: power on
38
A_SEL0
O
Analog audio selection signal output terminal “L”: external analog input, “H”: Bluetooth
39
HOLD
I
Fixed at “L” in this unit
40
WL_SCL
O
Not used
41
WL_SDA
O
Not used
42
BT_RST
O
Reset signal output to the Bluetooth module “L”: reset
43
PCONT_BT
O
+3.3V power on/off control signal output terminal for the Bluetooth section “H”: power on
44
WR
I
Fixed at “H” in this unit
45
HDMI_SDA
I/O
Two-way I2C data bus with the HDMI transceiver
46
HDMI_SCL
O
I2C clock signal output to the HDMI transceiver
47
HDMI_MUTE_DET
I
HDMI muting on/off control signal input from the HDMI transceiver “H”: muting on
48
DSP_SPIDS
O
Chip select signal output to the serial fl ash and DSP
49
DSP_RESET
O
Reset signal output to the DSP “L”: reset
50
SF_HOLD_DSP
O
Hold signal output to the serial fl ash “L”: hold
51
DIR_HCE
O
Chip enable signal output to the digital audio interface receiver
52
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
53
DIR_RST
O
Reset signal output to the digital audio interface receiver “L”: reset
54
HDMI_RST
O
Reset signal output to the HDMI transceiver “H”: reset
55
HDMI_MUTE_ON
O
HDMI muting on/off control signal output terminal “H”: muting on
56
HDMI_INT
I
Interrupt signal input from the HDMI transceiver
57
SEL_HDMI
O
HDMI selection signal output terminal “H”: HDMI
MAIN BOARD IC1002 R5F3650NCDFB (SYSTEM CONTROLLER)
HT-XT1
55
Pin No.
Pin Name
I/O
Description
58
RST_FL
O
Reset signal output to the fl uorescent indicator tube “L”: reset
59
P_CONT3
O
Power on/off control signal output terminal “H”: power on
60
Vcc2
-
Power supply terminal (+3.3V)
61
PCON_IR
O
Not used
62
Vss
-
Ground terminal
63
PW_VACS_DET
I
Thermal detection signal input terminal Not used
64
P_CONT1
O
Power on/off control signal output terminal “H”: power on
65
WS_INT
O
Not used
66
DSP_INTR
I
Interrupt request signal input from the DSP
67
DAMP_SOFT_MUTE
O
Soft muting on/off control signal output to stream processor “L”: muting on
68
DAMP_INIT
O
Reset signal output to the stream processor “L”: reset
69
DAMP_PDN
O
Power down signal output to the stream processor “L”: power down
70
AMP_OVF
I
Overfl ow detection signal input from the digital power amplifi er
71
AC_CUT
I
AC cut detection signal input terminal “L”: AC cut is detected
72
KEY_INT
I
Key wake-up signal input terminal
73
BT_MUTE
I
Muting on/off control signal input from the Bluetooth module “L”: muting on
74
DC_DET
I
Speaker DC detection signal input terminal “L”: speaker DC is detected
75
FL_DATA
O
Serial data output to the fl uorescent indicator tube
76
FL_CS
O
Chip select signal output to the fl uorescent indicator tube
77
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube
78
P_CONT_HDMI
O
Power on/off control signal output terminal for the HDMI section “H”: power on
79
CP_RESET
O
Reset signal output to the MFI “L”: reset
80
P_CON_DSP
O
Power on/off control signal output terminal for the DSP “H”: power on
81
SW_NFC
O
Standby control signal output to the NFC module “L”: standby
82
LED_PW
O
LED drive signal output terminal for the illumination (white) “H”: LED on
83
IRQ_NFC
I
Radio data reception signal input from the NFC module
84
SEL_NFC
O
Data transmission direction and completion notice signal output to the NFC module
85
DATA_NFC
O
Serial data output the NFC module
86
SPICLK_NFC
O
Serial data transfer clock signal output to the NFC module
87
CP_CLK
O
Serial data transfer clock signal output to the MFI
88
CP_DATA
I/O
Two-way data bus with the MFI
89
LED_MUTE
O
Not used
90
DESTINATION
I
Destination setting terminal
91
MODEL
I
Model setting terminal
92
KEY2
I
Key input terminal Not used
93
KEY1
I
Power touch key input from the touch key controller
94
AVss
-
Ground terminal
95
KEY0
I
Touch key input from the touch key controller
96
Vref
I
Reference voltage (+3.3V) input terminal
97
AVcc
-
Power supply terminal (+3.3V)
98
DIR_DO
(MC_DIRDI)
I
Serial data input from the digital audio interface receiver
99
DIR_DI
(MC_DIRDO)
O
Serial data output to the digital audio interface receiver
100
DIR_CLK
O
Serial data transfer clock signal output to the digital audio interface receiver
HT-XT1
56
MAIN BOARD IC2009 ADSST-AVR-3045 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDD_INT
-
Power supply terminal (+1.1V) (for core)
2
CLK_CFG1
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “L” in this unit
Fixed at “L” in this unit
3
BOOT_CFG0
I
Boot mode selection signal input terminal Fixed at “H” in this unit
4
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
5
VDD_INT
-
Power supply terminal (+1.1V) (for core)
6
BOOT_CFG1
I
Serial data input from the system controller
7
GND
-
Ground terminal
8, 9
NC
-
Not used
10
CLK_CFG0
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “L” in this unit
Fixed at “L” in this unit
11
VDD_INT
-
Power supply terminal (+1.1V) (for core)
12
CLKIN
I
System clock input terminal (25 MHz)
13
XTAL
O
System clock output terminal (25 MHz)
14
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
15, 16
VDD_INT
-
Power supply terminal (+1.1V) (for core)
17
RESETOUT/
RUNRSTIN
I/O
Reset signal output and running reset signal input terminal Not used
18
VDD_INT
-
Power supply terminal (+1.1V) (for core)
19
MOSI
I
Serial data input from the system controller
20
MISO
O
Serial data output to the system controller
21
SPICLK
I
Serial data transfer clock signal input from the system controller
22
VDD_INT
-
Power supply terminal (+1.1V) (for core)
23
DPI_P05
I
Chip select signal input from the system controller
24
DSP_CS
I
Chip select signal input from the system controller
25
MD
-
Not used
26
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
27
DPI_P08
-
Not used
28
RESET_MAIN
-
Not used
29
VDD_INT
-
Power supply terminal (+1.1V) (for core)
30
UART_OUT
O
Serial data output to the system controller
31
UART_IN
I
Serial data input from the system controller
32
LED
-
Not used
33
DPI_P12
-
Not used
34
DPI_P13
-
Not used
35
DAI_P03
-
Not used
36
DPI_P14
-
Not used
37 to 39
VDD_INT
-
Power supply terminal (+1.1V) (for core)
40
SL/SR_IN
I
Audio signal (for surround L-ch/R-ch) input from the digital audio interface receiver
41
SL/SR_OUT
O
Audio signal output terminal Not used
42
BCLK_IN
I
Bit clock signal input from the digital audio interface receiver
43
OPTION_L/
OPTION_R_OUT
O
Audio signal output terminal Not used
44
FRONTHI_L/R_OUT
O
Audio signal output terminal Not used
45
VDD_INT
-
Power supply terminal (+1.1V) (for core)
46
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
47
VDD_INT
-
Power supply terminal (+1.1V) (for core)
48
L/R_OUT
O
Audio signal (for front L-ch/R-ch) output to the stream processor
49
MID/SW2_OUT
O
Audio signal output terminal Not used
50
SBL/SBR_OUT
O
Audio signal output terminal Not used
51
ZONE_L/R
I/O
Not used
52
VDD_INT
-
Power supply terminal (+1.1V) (for core)
53
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
54
MCLK_IN
I
Master clock signal input from the digital audio interface receiver
55
VDD_INT
-
Power supply terminal (+1.1V) (for core)
56
C/SW1_OUT
O
Audio signal (for subwoofer) output to the stream processor
57
A/D_2CH
I
Audio signal input from the digital audio interface receiver
58
C/SW_IN
I
Audio signal (for center and subwoofer) input from the digital audio interface receiver
59
LRCLK_IN
I
L/R sampling clock signal input from the digital audio interface receiver
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