Sony HT-SS600 (serv.man2) Service Manual ▷ View online
37
STR-KS600P
Pin No.
Pin Name
I/O
Description
48
VSS
-
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode
Fixed at "H" in this set
Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use
Fixed at "L" in this set
Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+2.6V)
61
VSS
-
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal Not used
68
DECODE
O
Read ready signal output to the system controller
69
AUDIO
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+2.6V)
71
VSS
-
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+2.6V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
38
STR-KS600P
Pin No.
Pin Name
I/O
Description
117
TST2
I
Not used
118
GP11
I
Not used
119
TST3
I
Not used
120
VDDI
-
Power supply terminal (+2.6V)
39
STR-KS600P
PLACA DIGITAL IC1601 MB90488BPF-G-111E1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATAO
I
Audio serial data input from the digital audio interface receiver
2
GP9
I
Read ready signal input from the DSP
3
BST
O
Boot strap signal output to the DSP
4
HCS
O
Chip select signal output to the DSP
5
HACN
I
Acknowledge signal input from the DSP
6
XRST
O
System reset signal output to the DSP "L": reset
7
PM
O
PLL initialize signal output to the DSP
8
PWM-DA
O
Power control signal output terminal
9
GP12
O
Write signal output to the DSP
10
AD_RST
O
Reset signal output to the A/D converter
11
VSS
-
Ground terminal
12, 13
VIDEO-SW1,
VIDEO-SW2
O
Video input selection signal output terminal Not used
14
VIDEO-MUTE
O
Video muting on/off control signal output terminal Not used
15, 16
157_CTL1,
157_CTL2
-
Not used
17
WOOFER RELAY
-
Not used
18
HDOUT
I
Serial data input from the DSP
19
HDIN
O
Serial data output to the DSP
20
HCLK
O
Serial data transfer clock signal output to the DSP
21, 22
SELECT_B,
SELECT_A
O
Analog audio input signal switching signal output terminal
23
VCC5
-
Power supply terminal (+3.3V)
24
ANA/DIG
O
Analog/digital selection signal output terminal "L": analog, "H": digital
25
14052_CTL1
-
Not used
26
POWER_SD
I
Over load detection signal input terminal
27, 28
FLASH2,
FLASH1
O
Flash programming signal output terminal Not used
29
NC
-
Not used
30
XSCEN
O
Chip enable signal output terminal Not used
31
XRST
O
System reset signal output terminal Not used
32
POWER_RST
O
Reset signal output to the digital power amplifiers
33
SCL
O
Serial data transfer clock signal output to the EEPROM
34
SDA
I/O
Two-way data bus with the EEPROM
35
AVCC
-
Power supply terminal (+3.3V)
36
AVRH
I
Reference voltage (+3.3V) input terminal
37
AVSS
-
Ground terminal
38 to 40
A/D0 to A/D2
I
Front panel key input terminal (A/D input)
41
A/D3
I
Key input terminal Not used
42
VSS
-
Ground terminal
43
RDS SIGNAL
I
RDS signal input from the tuner unit (AEP, UK models)
44
MODEL
I
Setting terminal for the model (A/D input)
45
VERSION
I
Setting terminal for the destination (A/D input)
46
P. CONT1
O
Power on/off control signal output terminal
47
SMPS RST
-
Not used
48
STOP P. STOP
I
AC off detection signal input terminal "L": AC off
49 to 51
MD0 to MD2
I
CPU operation mode setting signal terminal
40
STR-KS600P
Pin No.
Pin Name
I/O
Description
52
RDS CLK
I
RDS interrupt clock signal input from the tuner unit (AEP, UK models)
53
RDS DATA
I
RDS serial data input from the tuner unit (AEP, UK models)
54
SIRCS
I
SIRCS signal input terminal
55
FUSE DETECT
I
Fuse open detection signal input terminal "L": fuse opened
56
POWER KEY
I
Power key input terminal "L": switch on
57
NO USE
-
Not used
58 to 60
LAT3 to LAT1
O
Latch signal output to the stream processor
61
SHIFT
O
Serial data latch pulse output to the stream processor
62
SCDT
O
Serial data output to the stream processor
63
SOFT_MUTE
O
Muting on/off control signal output terminal
64
INT
O
Initialize signal output to the stream processor
65
STEREO
I
FM stereo detection signal input from the FM/AM tuner pack
66
TUNED
I
Tuned detection signal input from the FM/AM tuner pack
67
TUNER_LED
O
LED drive signal output terminal
68
OVF
I
Overflow signal input from the stream processor
69
FAN_CTL
O
Fan motor on/off control signal output terminal Not used
70, 71
VOLB, VOLA
I
Jog dial pulse input terminal
72
FL_DATA
O
Serial data output to the fluorescent display tube driver
73
FL_CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube driver
74
FL_STB
O
Strobe signal output to the fluorescent indicator tube driver
75
FAN_CLK
I
Fan motor feedback clock signal input terminal Not used
76
FAN_ON
I
Fan motor level detection signal input terminal Not used
77
RSTX
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
78
OVFW
I
Overflow signal input for subwoofer from the stream processor
79
X1A
O
Sub system clock output terminal Not used
80
X0A
I
Sub system clock input terminal Not used
81
VSS
-
Ground terminal
82
X0
I
Main system clock input terminal (24 MHz)
83
X1
O
Main system clock output terminal (24 MHz)
84
VCC3
-
Power supply terminal (+3.3V)
85
T. CLK
O
Serial data transfer clock signal output to the FM/AM tuner pack
86
T. DATA
O
Serial data output to the FM/AM tuner pack
87
SLATCH
O
Latch signal output to the FM/AM tuner pack
88
T_DO
I
Serial data input from the FM/AM tuner pack
89
T_MUTE
O
Muting on/off control signal output terminal
90, 91
TC74AC_A,
TC74AC_B
-
Not used
92
LRCK_SW
O
L/R sampling clock signal switching signal output terminal
93
XMODE
O
System reset signal output to the digital audio interface receiver "L": reset
94
CKSEL1
O
Output clock selection signal output terminal Not used
95
CLK
O
Clock signal output to the digital audio interface receiver
96
CE
O
Chip enable signal output to the digital audio interface receiver
97
D1
O
Write data output to the digital audio interface receiver
98
D0
I
Read data input from the digital audio interface receiver
99
ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
100
XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
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