Sony HT-SS380 / STR-KS380 Service Manual ▷ View online
STR-KS380
STR-KS380
9
9
5-1. BLOCK DIAGRAM - MAIN Section -
SYSTEM CONTROLLER
IC1008 (1/4)
DIGITAL OPTICAL
RECEIVER
IC1700
14
L CH
R CH
TUNER L
11
28
15
14
14
24
23
25
26
23
25
26
RST 34
16
DIR_MOSI
DIR_SIGNAL
DIR_MISO
DIR_CLK
DIR_CE
DIR RESET
DIR_MPOI
DIR_MPOO
DIR_MOSI
DIR_SIGNAL
DIR_MISO
DIR_CLK
DIR_CE
DIR_RESET
DIR_MPOI
DIR_MPOO
15
DOUT 17
BCK 19
LRCK 18
14
13
12
13
12
1
2
SCKO
SI_A_B_DOUT
SI_F
MCK
BCK
LRCK
SD0
SD1
SD2
SD3
SPDIF
ACR
SL_E
SL_D
ERROR
NPCM
DZR_XSTATE
BCK
LRCK
MCK
20
AUDIO 7
5
6
8
9
10
28
29
47
13
4
OPT IN TV
DIGITAL OPTICAL
RECEIVER
IC1701
OPT IN
SAT/CATV
DIGITAL AUDIO
INTERFACE RECEIVER
IC1705
J1702
COAX IN
VIDEO
FM 75
:
COAXIAL
11
10
10
DIGITAL
AUDIO IN
LINE IN
ANTENNA
J1701
IC1709
TUNER
L
R
DMPORT L
15
R-CH
ANALOG AUDIO
INPUT SELECTOR
IC1707
R-CH
25
40
39
X1700
24.576MHz
XOUT(O)
XIN(I)
FM ANT
LINE AMP
IC1708
8
9
8
10
16
13
13
15
Xout
Xin
X1001
5MHz
18
19
X1701
32.768MHz
A
x SIGNAL PATH
: TUNER
: AUDIO (ANALOG)
: AUDIO (DIGITAL)
x R-ch is omitted due to same as L-ch.
30
31
AUTO
CAL MIC
J1700
CN1702
DCAC L
12
DCAC L 6
DCAC R
76
CEC DATA
SWITCH
Q1003 – Q1006
55
UCOM RX-HDMI_TX
UCOM TX-HDMI_RX 56
UCOM TX-HDMI_RX 56
HDMI_RST
HTXD
HRXD
HRESET
57
63
58
58
CEC
D
30 29 31 39
38 19
37 36
HDMI_CNVSS
HDMI_CNVSS
64
HRESET,
HTXD, HRXD
E
: MIC
3
J
HDMISPDIF
MUTE
SWITCH
Q1704
SELECT B
SWITCH
Q1702
SELECT A
SWITCH
Q1703
GAIN CONTROL
Q1700
DCAC L 9
DCAC L 10
A+9V
SC_SHIFT, SC_SCDT
P
SC_SHIFT
SC_SCDT
WAVE SHAPPER
IC1704
33
7
6
2
1
3
1
MIC AMP
IC1703
5
7
LINE AMP
IC1711
5
4
7
68
67
(PAGE 10)
N
(PAGE 11)
(PAGE 11)
(PAGE 12)
DIR_RESET
C (PAGE 11)
(PAGE 10)
(PAGE 10)
U (PAGE 10)
X1
X2
IIC/RDSI
CK
DA
IISD
SI_A_B_DOUT, MCK, BCK, LRCK,
SI_F, SL_E, SL_D, ERROR,
NPCM, DZR_XSTATE
ERROR/INT0
NPCM/INT1
SI_E
SI_F
MPIO_B1/SI_D
MPIO_A0/HDMI_MCK
MPIO_A1/HDMI_BCK
MPIO_A2/HDMI_LRCK
MPIO_A3/SD0
MPIO_C1/SD1
MPIO_C2/SD2
RXIN7/HDMI_SPDIF
RXIN6/HDMI_ARC
MPIO_C3/SD3
VINL
MDO/ADR0
MDI/SDA
MC/SCL
MS/ADR1
MPO0
MPO1
X_OUT_L
AUDIO_L
FRF1
ROUT
LOUT
TUN_SCL
TUN_SD
TUN_SDA
TUN_RDSI
SELECT_A
SELECT_B
MUTE_ANA_SEL
DIR_MISO
COM_DA
TA
DIR_SIGNAL
COM_CLK
DIR_MPO0
DIR_MPO1
DIR_RST
DIR_CE
HDMI_CECDO
HDMI_CECDI
RXIN5/TV OPT IN
RXIN4/SAT OPT IN
RXIN2/VIDEO_Coaxial In
US, CND
DSP_MOSI
DSP_MOSI
MC/SCL
DSP_MOSI
STR-KS380
STR-KS380
10
10
5-2. BLOCK DIAGRAM - HDMI PC Section -
(PAGE 11)
(PAGE 11)
(PAGE 9)
(PAGE 13)
(PAGE 9)
(PAGE 9)
(PAGE 9)
(PAGE 13)
D
J
G
E
U
K
R
Q
HDMI CONTROLLER
IC3000
CN3503
GAME IN
R1X0+
121
R1X0-
120
7
9
9
R1X1+
123
R1X1-
122
4
6
6
R1X2+
125
R1X2-
124
1
3
3
R1XC+
119
R1XC-
118
10
DATA0+
DATA0–
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
15
HDMI
INPUT
SELECTOR
IC3500
RX-RST
RX-INT
DSDA1
36
19
HPD1
R1PWR5V
34
33
DSCL1
35
CN3502
BD/DVD IN
HDMI
R2X0+
130
R2X0-
129
7
9
9
R2X1+
132
R2X1-
131
4
6
6
R2X2+
134
R2X2-
133
1
3
3
R2XC+
128
R2XC-
127
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
15
DSDA2
40
19
HPD2
38
R2PWER5V
37
DSCL2
39
CN3501
R3X0+
139
R3X0-
138
7
9
9
R3X1+
141
R3X1-
140
4
6
6
R3X2+
143
R3X2-
142
1
3
3
R3XC+
137
R3XC-
136
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
15
DSDA3
44
19
HPD3
R3PWR5V
RESET#
INT
CSDA
CSCL
42
41
SBVCC5
28
21
22
23
24
MUTEOUT 107
DSCL3
43
HDMI
TRANSMITTER
IC3501
MUTE
TX_INT
TX_RST
CSCL
CSDA
56 – 63, 67 - 75,
77 – 86, 90 – 98
D0 – D35
TX0+ 34
TX0– 33
TX0– 33
7
9
9
TX1+ 37
TX1– 36
TX1– 36
4
6
6
TX2+ 40
TX2– 39
TX2– 39
1
3
3
TXC+ 31
TXC– 30
TXC– 30
10
HPD
DATA0+
DATA0–
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
SCL (5V)
HOT PLUG DET
CEC
51
19
14
12
16
15
15
13
DSDA 47
DSCL 46
INT 24
RESET 25
CSDA 49
CSCL 48
CN3500
TV OUT
HDMI
HDMI_SPDIF
10
RESET
HRESET,
HTXD, HRXD
51-59,62-70,
77-85,88-96
Q0-Q35
13
11
XIN
XOUT
X3000
10MHz
33
TX
34
RX
CEC
MUTE
HDMI_CNVSS
41
TX_5VPWR
5VPWR
HRXD
HRESET
HTXD
SAT/CATV IN
BUFFER
IC3507
SD0 – SD3, MCK,
BCK, LRCK
SCK
WS
SPDIF
MCK
SD1
SD0
SD3
SD2
SD3
SD2
WS
SCK
WS
SPDIF
MCK
99
100
105
SD2
SD1
SD3
102
SD0 101
103
104
104
106
7
19
6
20
10
16
10
16
18
8
17
9
SD1
SD0
SD0
DLO
SD1
DR1
SD2
SD2
DL1
SD3
SD3
DR2
WS
DR0
SCK
SCK
DCLK
SPDIF
SPDIF
DL2
SPDIF
SCK
MCK
MCLK
11
15
15
4
21
5
SD0
SD1
SD2
SD3
WS
SCK
SD1
SD2
SD3
WS
SCK
MCK
SPDIF
SD0 – SD3
LRCK
ARC
BCK
MCK
MCK
D3001
D3000
BUFFER
IC1014
10
9
6
1
7
29
30
7
232C_OUT(VU TX)
FLUSH 1
SELECT
232C_IN(VU RX)
232COUT(VUTX)
232CIN(VURX)
CNVSS
VSYNC
DE
ODCK
HSYNC
HSYNC
VSYNC
ODCK
74
DE 73
75
76
76
VSYNC
DE
ODCK
HSYNC
HSYNC
VSYNC
IDCK
3
DE
1
2
88
UART_OUT
UART_IN
UART_IN
RESET
CNVSS
2
CN3000
1
5
3
3
4
5
6
4
5
6
13
12
11
12
11
18
7
8
2
8
2
9
14 – 17
10
5
4
XIN
XOUT
X3501
27MHz
(NC)
2
3
3Y
2A
IC3527
LEVEL SHIFT
RESERVE(NC)
Non LPCM
LPCM
MUTE
19 20
27 28
65
43
42
64
SIGNAL PATH
: AUDIO (DIGITAL)
: HDMI
STR-KS380
STR-KS380
11
11
5-3. BLOCK DIAGRAM - DISPLAY Section -
E2P_SCLK
E2P_SDA
A
SI_F
SI_A_B_DOUT
ERROR
SL_D
SL_E
BCK
NPCM
DZR_XSTATE
LRCK
MCK
DIGITAL AUDIO
INPUT SELECTOR
IC1710
2
5
12
3
13
1
15
4
10
9
11
14
MUTING
Q1701
G
NPCM, MUTE
59
60
61
4 54
81
78 57 58
27
24
26
42
SYSTEM CONTROLLER
IC1008 (2/4)
96
97
95
101
100
103
103
92
74
75
136
135
DIGITAL AUDIO
INTERFACE RECEIVER
IC1009
86
SWITCHING
IC1002
1
2
5
3
7
6
MUTING
Q1001
99
98
73
94
SWITCH
IC1000
EEPROM
IC1006
+5V REGULATOR
IC1010
AMP_BCK1
AMP_LRCK1
AMCK1
AMP_DATA1 – AMP_DATA3,
AMP_BCK1, AMP_LRCK1, AMCK
H
AMP_DATA1
AMP_DATA2
AMP_DATA3
23 22 20 18 19
7
1
6
2
5
25
24
X1000
25MHz
MEU
TMS
TCK
TRST
TMS
TCK
TRST
TD0
TD1
CLKIN
NPCM
MUTE
SIGNAL PATH
: AUDIO (DIGITAL)
: AUDIO (ANALOG)
BUFFER
IC1007
14
13
13
12
2
3
3
4
5
6
6
7
DMPORT RX (UCOM TX)
DMPORT TX (UCOM RX)
6
5
CN1700
49
48
DET
7
CLK1
CNVSS
RESET
RTS1
RXD1
5
6
CN1002
TXD1
4
3
50
DMPORT
FLASH PROGRAMMING
7
8
9
(PAGE 9)
(PAGE 12)
(PAGE 10)
Lch
Rch
14
13
R-CH
N (PAGE 9)
146
174
164
144
158
151
174
164
144
158
151
14
38
39
40
42
43
38
39
40
42
43
134
46 47
5
6
MEU
TMS
TCK
TRST
TMS
TCK
TRST
TD0
TD1
21
SI_A_B_DOUT, MCK, BCK, LRCK,
SI_F, SL_E, SL_D, ERROR,
NPCM, DZR_XSTATE
DC OFFSET DET
Q1007
RESET SWITCH
Q1002
49
50
50
44
47
47
173
1
2
2
D1005
(PAGE 10)
FLUSH 1
SELECT
R
(PAGE 9)
C
UART_OUT
UART_IN
DIR_RESET
SBL/SBR_IN
MCLK_IN
C/SW_IN
LRCLK_IN
BCLK_IN
SL/SR_IN
FLAG1
FLAG2
XTAL2
UART_OUT
UART_IN
UART_IN
MD
RESET_MAIN
SL/SR_OUT
SL/SR_OUT
L/R_OUT
C/SW1_OUT
BCLK_OUT
LRCLK_OUT
EMU
TCK
TMS
TRST
TDI
TDO
BOOT_CFG1
SPICLK
DPI_P05
MOSI
MISO
MISO
DSP_CS
IRQ/GPIO
1A
1B
2Y
2A
2B
1Y
B3
A3
AO
BO
SO
HOLD#
Vdd
WP#
Vss
1Y
0Y
1Z
Z-OUT
0Z
0X
1X
X-OUT
Y-OUT
Select Z
Select Y
Select X
SI(FLASH2)
SO(FLASH1)
PGCLK(FLASH)
DIR_XST
ATE
DSP_ERROR
DSP_SEL_MUL
TI
DSP_NPCM
DSP_RST
DSP_MISO
DSP_MOSI
DSP_SPICLK
DSP_SPICS
DSP_SFLASH_HOLD
US
1
CN1004
3
4
5
6
7
CN1003
3
4
5
6
4
1
2
BUFFER
IC1012
AND GATE
IC1013
RESET SIGNAL
GENERATOR
IC1003
TUNER
IC1015
4
1
2
2
4
1
1
A/D_2CH
L/R_IN
DIR_IN
A1
B1
B1
Y3
YO
Y1
OUT
OUT
IN
IN
IN
OUT
Gate
In A
OUT_Y
DMPORT_DET
DMPOR
T_RX_UCOM _TX
DMPORT_TX_UCOM_RX
P01_PROGRAMMING
HDMI_RST
HDMI_CECDI
DSP_UAR
T_SELECT
RST
AC_CUT
STR-KS380
STR-KS380
12
12
5-4. BLOCK DIAGRAM - AMP Section -
+
H
AMP_DATA1 – AMP_DATA3,
AMP_BCK1, AMP_LRCK1, AMCK1
L
SD
AMP_BCK1
AMP_DATA1
AMP_DATA2
DIGITAL POWER AMP
IC2005
STREAM PROCESSOR
IC2000
31 DATA1
OVER LOAD
DETECT
Q2005
SYSTEM CONTROLLER
IC1008 (3/4)
30 BCK
AMP_LRCK1
29 LRCK
36 XFSIIN
21 SCDT
21 SCDT
SC_SCDT
AMCK1
AMP_DATA3
22 SCSHIFT
SC_SHIFT
23 SCLATCH
LAT1
27 INIT
INIT
24 OVF FLAGR
25 OVF FLAGL
25 OVF FLAGL
OVF FLAGL
OVF FLAGL
OVFW
X2000
49.152MHz
L.P.F.
L.P.F.
OVF1
19 SOFT MUTE
SOFT_MUTE
18 NSP MUTE
20 PGMUTE
20 PGMUTE
PGMUTE
NSPMUTE
19 SOFT MUTE
SOFT_MUTE
19 SOFT MUTE
SOFT_MUTE
OUTL1(+) 11
OUTL2(–)
9
OUTR1(+)
6
OUTR2(–)
4
XFSOIN 48
FSOCKO 37
XFSOOUT 14
FSOI 38
STREAM PROCESSOR
IC2001
31 DATA2
30 BCK
29 LRCK
36 XFSIIN
21 SCDT
21 SCDT
SC_SCDT
22 SCSHIFT
SC_SHIFT
23 SCLATCH
LAT2
27 INIT
INIT
24 OVF FLAGR
25
25
OUTL1(+) 11
OUTL2(–)
9
OUTR1(+)
6
OUTR2(–)
4
XFSOIN 48
XFSOOUT 14
FSOI 38
STREAM PROCESSOR
IC2002
31 DATA3
30 BCK
29 LRCK
36 XFSIIN
21 SCDT
21 SCDT
SC_SCDT
22 SCSHIFT
SC_SHIFT
23 SCLATCH
LAT3
27 INIT
INIT
18 NSP MUTE
20 PGMUTE
20 PGMUTE
NSP_MUTE
PGMUTE
PGMUTE
24 OVF FLAGR
LAT1
LAT2
LAT3
LAT2
LAT3
INIT
25
OUTR1(+)
6
OUTR2(–)
4
OUTL1(+) 11
OUTL2(–)
9
XFSOIN 48
FSOI
CLOCK
BUFFER
IC2004
FRONT L
+
_
_
_
_
_
OVER LOAD
DETECT
Q2003
L.P.F.
L.P.F.
FRONT R
+
TB2002
TB2001
+
_
OVER LOAD
DETECT
Q2007
OVER LOAD
DETECT
Q2009
OVER LOAD
DETECT
Q2011
L.P.F.
L.P.F.
SUR L
SPEAKERS
SUR R
SUBWOOFER
+
OVER LOAD
DETECT
Q2013
L.P.F.
L.P.F.
CENTER
+
DIGITAL POWER AMP
IC2007
L.P.F.
L.P.F.
DIGITAL POWER AMP
IC2006
/SD
PWM_A
OUT_C
OUT_D
6
PWM_B
8
31
28
5
/RESET
7
DC DETECT
Q2017
DAMP_LATCH1
DAMP_LATCH2
DAMP_LATCH3
DAMP_LATCH3
69
70
71
70
71
DAMP_INIT 97
OVF1
OVERFLOW1 88
OVFW
OVERFLOW2 89
SOFT_MUTE
SOFT_MUTE 100
NSP_MUTE
NSP_MUTE 99
DRIVE_OCP 74
DC_DET 83
DRIVE _RST(EN) 98
L.P.F.
L.P.F.
PWM_D
OUT_B
OUT_A
16 PWM_C
18
39
36
/RESET
17
/SD
PWM_C
OUT_C
OUT_D
16
PWM_D
18
31
28
5
/RESET
7
PWM_B
OUT_B
OUT_A
6
PWM_A
8
39
36
/RESET
17
/SD
PWM_C
OUT_C
OUT_D
16
PWM_D
18
31
28
5
/RESET
7
PWM_A
OUT_B
OUT_A
6
39
PWM_B
8
36
/RESET
17
18 NSPMUTE
20 PGMUTE
20 PGMUTE
NSPMUTE
PGMUTE
PGMUTE
PROTECT DETECT
Q2018 – 2019
+31.5V
RESET
Q2020 – 2021
+3.3V
AMP_BCK1
AMP_LRCK1
AMCK1
AMP_BCK1
AMP_LRCK1
AMCK1
P
SC_SHIFT,
SC_SCDT
SC_SCDT
(PAGE 11)
(PAGE 9)
(PAGE 13)
6,*1$/3$7+
: AUDIO (DIGITAL)
38
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