Sony HT-SS1000 Service Manual ▷ View online
33
STR-KS1000
IC901
STR-F6168-LF1352
OVER
CURRENT
PROTECT
2
LOGIC
OSC
INTERNAL BIAS
DELAY
DELAY
LATCH
CURRENT
MIRROR
OVER
CURRENT
PROTECT
2
OVER
CURRENT
PROTECT
1
FEED
BACK
INH
2
INH
1
BOTTOM
SKIP
LOGIC
OCP/INH
1
S/GND
2
DRAIN
3
VCC
4
FB/OCP
5
UNDER VOLTAGE
LOCK OUT
OVER LOAD
PROTECT
THERMAL
SHUT DOWN
OVER VOLTAGE
PROTECT
SWITCHING
REGULATOR
BLOCK
IC921
STR-V153
5
8
4
1 2 3
GND
6
FB/OLP
7
N.C.
STARTUP
VCC
D
N.C.
SOURCE/OCP
+
−
–
+
+
−
+
−
+
−
+
−
+
−
Q S
R
DISCHARGE
BLANKING
BUFFER
TSD
DELAY
LATCH
INTERNAL
BIAS
OFF TIMER
PRC LATCH
BURST
FB
OCP
OLP
DRIVE
OVP
UVLO
POWER
MOS FET
34
STR-KS1000
IC941
SI-3120KM-TL
IC942
SI-3050KM-TL
IC943
SI-3033KM-TL
1
VC
TSD
2
VIN
3
GND
4
VOUT
5
ADJ
+
–
REF
IC1301
LC89056W-E
38
37
36
23
24
1
2 3
4
5
44
8 9 10
46
17
22
21
20
30
35
25
26
27
28
29
32
33
34
16
45
13
14
15
47
40
41
48
CL
39
XSEL
CE
DI
EMPHA
AUDIO
DISEL
DOUT
DINO
DINI
DIN2
6
DGND
7
DVDD
11
AVDD
12
AGND
DOSEL0
R
VIN
LPF
CKSEL0
XSTATE
18 DGND
19 DVDD
XIN
XOUT
XMCK
XSEL
31
DGND
DO
CSFLAG
F0
F1
F2
VF
ERR9P
BPSYNC
ERROR
DATAO
DOSEL1
CKOUT
BCK
LRCK
CKSEL1
MODE0
MODE1
42
DGND
43
DVDD
XMODE
TIMING
MICROCOMPUTER
INTERFACE
SAMPLING
FREQUENCY
C BIT
DETECT
PA/PB
DETECT
LOCK
DETECT
INPUT
CIRCUIT
DATA
DEMODULATOR
PLL
X’ TAL
IC1503
TC7WH157FU (TE12R)
SELECT
11
6
ST
11
7
A
1
2
3
A
B
Y
5
Y
B
GND 4
VCC
8
Y
EN G
Y
IC1602
PCM1803DBR
DELTA-SIGMA
MODULATOR
DELTA-SIGMA
MODULATOR
VINL 1
VINR 2
VREF1 3
VREF2 4
VCC
AGND
5
6
BYPAS 8
TEST 9
LRCK 10
REFERENCE
×
1/64,
×
1/128
DECIMATION
FILTER
WITH
HIGH-PASS
FILTER
SERIAL
INTERFACE
&
MODE/FORMAT
CONTROL
MODE1
20
MODE0
19
FMT1
18
FMT0
17
OSR
16
SCKI
15
VDD
14
DGND
13
DOUT
12
BCK
11
CLOCK & TIMING CONTROL
POWER
SUPPLY
PDWN 7
35
STR-KS1000
– HDMI Board –
IC5002
TK11150CSCL-G
5
1
2
3
REG
4
VOLTAGE
CONTROL
COMP
VIN
VOUT
CONTROL
GND
NOISE
BYPASS
IC5006
BA00BC0WFP-E2
THERMAL
SHUT DOWN
OVER CURRENT
PROTECT
VDD
VCC
2
GND
3
NC
5
OUT
4
CTL
1
–
+
VREF
DRIVER
– Placa DISPLAY –
IC700
µ
PD16315GB-3BS
5
OSC
OSC
DATA
SELECTOR
6
DOUT
7
DIN
8
CLK
9
STB
10
KEY1
11
KEY2
SERIAL
INTERFACE
DISPLAY MEMORY
24 BITS x 12 WORDS
24-BIT OUTPUT
LATCH
12-BIT SHIFT
REGISTER
SEGMENT
DRIVER
TIMING GENERATOR
KEY SCAN
COMMAND
DECODER
DIMMING
CIRCUIT
KEY DATA MEMORY
(2 x 16 BITS)
4-BIT LATCH
1
LED1
2
LED2
3
LED3
4
LED4
24
16
16
12
4
8
8
4
8
27 SEG14/KS14
29 SEG16/KS16
30 VEE
28 SEG15/KS15
8
31 SEG17/GRID12
33 SEG19/GRID10
32 SEG18/GRID11
23 SEG10/KS10
24 SEG11/KS11
25 SEG12/KS12
26 SEG13/KS13
22
SEG9/KS9
21
SEG8/KS8
20
SEG7/KS7
19
SEG6/KS6
18
SEG5/KS5
17
SEG4/KS4
16
SEG3/KS3
15
SEG2/KS2
14
SEG1/KS1
MULTIPLEXED
DRIVER
34
SEG20/GRID9
35
SEG21/GRID8
36
SEG22/GRID7
37
SEG23/GRID6
39
GRID4
40
GRID3
41
GRID2
42
GRID1
43
VDD
44
VSS
13
VDD
12
VSS
38
SEG24/GRID5
GRID
DRIVER
36
STR-KS1000
•
DESCRIÇÕES DOS PINOS DE IC
PLACA PRINCIPAL IC1501 CXD9862R (DIGITAL AUDIO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
5
VDDI
-
Power supply terminal (+1.8V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input terminal Not used
7
PLOCK
O
PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.8V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock Fixed at "L" in this set
14
SCKOUT
O
Master clock signal output to the stream processor
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the stream processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the stream processor
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write enable signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+1.8V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output of data input/output mask to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
48
VSS
-
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
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