Sony HT-DDWG800 / STR-KG800 Service Manual ▷ View online
STR-KG800
53
• IC Pin Function Description
DIGITAL BOARD IC1009 ADSST-AVR-1115 (DSP)
DIGITAL BOARD IC1009 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V)
2, 3
CLKCFG0, CLKCFG1
I
Clock frequency setting terminal
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode setting terminal for DSP
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V)
14
GND
-
Ground terminal
15
FRAG1
O
Interrupt status output to the system controller
16
FRAG2
I
PLL lock error signal and data error fl ag input terminal
17
AD7
I/O
Two-way data bus and address signal output with S-RAM Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way data bus and address signal output with S-RAM Not used
27
VDDINT
-
Power supply terminal (+1.2V)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way data bus and address signal output with S-RAM Not used
31
VDDEXT
-
Power supply terminal (+3.3V)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way data bus and address signal output with S-RAM Not used
35
XWR
O
Data write enable signal output to the S-RAM "L": active Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V)
38
GND
-
Ground terminal
39
XRD
O
Read strobe signal output to the S-RAM "L": active Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way data bus and address signal output with S-RAM Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V)
46
AD12
I/O
Two-way data bus and address signal output with S-RAM Not used
47
VDDINT
-
Power supply terminal (+1.2V)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way data bus and address signal output with S-RAM Not used
53
A16
O
Address signal output to S-RAM Not used
54
VDDINT
-
Power supply terminal (+1.2V)
55
GND
-
Ground terminal
56, 57
A17, A18
O
Address signal output to S-RAM Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V)
60
VDDINT
-
Power supply terminal (+1.2V)
61
GND
-
Ground terminal
62
PF_CE
I/O
Chip enable signal input/output terminal Not used
63
SPI_MAS
O
Master/slave selection signal output terminal "L": DSP is master Not used
64
DPSOA
O
PCM audio signal (front L/R) output to the D/A converter
65
DPSOB
O
PCM audio signal (surround L/R) output to the D/A converter
66
VDDINT
-
Power supply terminal (+1.2V)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V)
69
GND
-
Ground terminal
70
DPSOC
O
PCM audio signal (center, sub woofer) output to the D/A converter
STR-KG800
54
Pin No.
Pin Name
I/O
Description
71
DPSOD
O
PCM audio signal (surround back L/R) output to the D/A converter
72
VDDINT
-
Power supply terminal (+1.2V)
73
VDDEXT
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V)
76
GND
-
Ground terminal
77
DPSOE
O
PCM audio signal output terminal Not used
78
DPSIA
I
PCM audio signal (digital input) input from the digital audio interface receiver
79
DPSIB
I
PCM audio signal (front L/R) input terminal
80
DPSIC
I
PCM audio signal (surround L/R) input terminal
81
DPSID
I
PCM audio signal (center, sub woofer) input terminal
82
DPSIE
I
PCM audio signal (surround back L/R) input terminal
83
VDDINT
-
Power supply terminal (+1.2V)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the D/A converter for PCM audio output
87
DPDVBCK
O
Bit clock signal output to the D/A converter for PCM audio output
88
DPLRCK
I
L/R sampling clock signal input terminal for PCM audio input
89
DPBCK
I
Bit clock signal input terminal for PCM audio input
90
VDDINT
-
Power supply terminal (+1.2V)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V)
94
DPFSCK
I
Master clock signal input terminal
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V)
97
XNONAUDIO
I
Digital input signal switch control signal input from the digital audio interface receiver
98
XSF_CE
O
Chip enable signal output terminal Not used
99
VDDINT
-
Power supply terminal (+1.2V)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V)
121
XRESET
I
System reset signal input from the system controller
122
XSPIDS
I
Serial data latch pulse signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V)
125
SPICLK
I/O
Serial data transfer clock signal input/output with the system controller
126
MISO
O
Serial data output to the main system controller
127
MOSI
I
Serial data input from the main system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V)
130
VDDEXT
-
Power supply terminal (+3.3V)
131
AVDD
-
Power supply terminal (+3.3V)
132
AVSS
-
Ground terminal
STR-KG800
55
Pin No.
Pin Name
I/O
Description
133
GND
-
Ground terminal
134
CLKOUT
-
Not used
135
XEMU
-
Not used
136
TDO
-
Not used
137
TDI
-
Not used
138
CTRST
-
Not used
139
TCK
-
Not used
140
TMS
-
Not used
141
GND
-
Ground terminal
142
CLKIN
I
System clock input terminal (25 MHz)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V)
STR-KG800
56
DIGITAL BOARD IC1010 MB91353APMT-G-117E1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAC CLK
O
Clock signal output to the D/A converter
2
XMDACMS
O
Serial data latch pulse signal output terminal Not used
3
XMDACMD1
O
Serial data output terminal Not used
4
DAC_D1
O
Serial data output to the D/A converter
5
TUNING A
I
Jog dial pulse input terminal Not used
6
TUNING B
I
Jog dial pulse input terminal Not used
7
HDMI_REG_CTRL
O
Power on/off control signal output terminal for the HDMI section "H": power on
8
DSP_SELECT
O
DSP select signal output to the switiching and data selector
9
POWER RY
O
Relay drive signal (for main power) output terminal "H": relay on
10
VOL_CL
O
Clock signal output to the electrical volume
11
VOL_DA
O
Serial data output to the electrical volume
12
HP_DETECT
I
Headphone detection signal input terminal "H": headphone is connected
13
HP_RY
O
Relay drive signal (for headphone) output terminal "H": relay on
14
C/SUR/SB
O
Relay drive signal (for center and surround) output terminal "H": relay on
15
FRONT B RY/
STER_SW
O
Relay drive signal (for front B) output terminal Not used
16
SW RY
O
Relay drive signal (for sub woofer) output terminal "H": relay on
17
FRONT A RY
O
Relay drive signal (for front A) output terminal "H": relay on
18
GND
-
Ground terminal
19
VCC
-
Power supply terminal (+3.3V)
20
SBR RY
O
Relay drive signal (for surround back) output terminal Not used
21
TUNE_LAT
O
Serial data latch pulse signal output to the tuner (FM/AM)
22
TUNE_DI
O
Serial data output to the tuner (FM/AM)
23
T_CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
24
TUNE_DO
I
PLL data input from the tuner (FM/AM)
25
FUSE_DETECT
I
Fuse detection signal input terminal
26
DAC_ATC
O
Serial data latch pulse signal output to the D/A converter
27
DAC_MUTE
O
Muting signal output to the D/A converter
28
CEC_OUT
O
CEC serial data output to the HDMI OUT connector
29
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
30
HDMI_ERR
I
HDMI audio error signal input terminal
31 to 34
V_SW4 to V_SW1
O
Video select signal output to the video amplifi er
35, 36
COMP_S1, COMP_S2
O
Component video select signal output to the video amplifi er
37
PS(V-MUTE)
O
Muting signal output to the video amplifi er
38
DIR_XMODE(RESET)
O
Reset signal output to the digital audio interface receiver "L": reset
39
DIRCKST
O
Clock selection signal output to the digital audio interface receiver
40
GND
-
Ground terminal
41, 42
NO USE
-
Not used
43
GND
-
Ground terminal
44
+3.3V
-
Power supply terminal (+3.3V)
45
DIR CLK
O
Serial data transfer clock signal output to the digital audio interface receiver
46
DIR CE(LAT)
O
Chip enable signal output to the digital audio interface receiver
47
DIR DI
O
Serial data output to the digital audio interface receiver
48
DIR DO
I
Serial data input from the digital audio interface receiver
49
DIR ERROR
I
PLL lock error signal and data error fl ag input from the digital audio interface receiver
50
HDMI_FSRATE
I
Serial data input terminal
51
NMI
I
Non maskable interrupt signal input terminal Not used
52
MD2
I
CPU operation mode setting signal input terminal "H": fl ash programming
53
MD1
I
CPU operation mode setting signal input terminal Not used
54
MD0
I
CPU operation mode setting signal input terminal Not used
55
INIT
I
External reset signal input terminal
56
+3.3V
-
Power supply terminal (+3.3V)
57
X1
O
Main system clock output terminal (24 MHz)
58
X0
I
Main system clock input terminal (24 MHz)
59
GND
-
Ground terminal
60
XOA
I
Sub system clock input terminal Not used
61
X1A
O
Sub system clock output terminal Not used
62
RST_TRG
O
Reset signal output terminal
63
DIR_DATA0
I
Serial data input from the digital audio interface receiver
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