Sony HT-CT380 / HT-CT381 / SA-CT380 / SA-CT381 Service Manual ▷ View online
HT-CT380/CT381
53
MAIN BOARD IC2009 ADSST-AVR-3045 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDD_INT
-
Power supply terminal (+1.1V) (for core)
2
CLK_CFG1
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “L” in this unit
Fixed at “L” in this unit
3
BOOT_CFG0
I
Boot mode selection signal input terminal Fixed at “H” in this unit
4
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
5
VDD_INT
-
Power supply terminal (+1.1V) (for core)
6
BOOT_CFG1
I
Serial data input from the system controller
7
GND
-
Ground terminal
8, 9
NC
-
Not used
10
CLK_CFG0
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “L” in this unit
Fixed at “L” in this unit
11
VDD_INT
-
Power supply terminal (+1.1V) (for core)
12
CLKIN
I
System clock input terminal (25 MHz)
13
XTAL
O
System clock output terminal (25 MHz)
14
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
15, 16
VDD_INT
-
Power supply terminal (+1.1V) (for core)
17
RESETOUT/
RUNRSTIN
I/O
Reset signal output and running reset signal input terminal Not used
18
VDD_INT
-
Power supply terminal (+1.1V) (for core)
19
MOSI
I
Serial data input from the system controller
20
MISO
O
Serial data output to the system controller
21
SPICLK
I
Serial data transfer clock signal input from the system controller
22
VDD_INT
-
Power supply terminal (+1.1V) (for core)
23
DPI_P05
I
Chip select signal input from the system controller
24
DSP_CS
I
Chip select signal input from the system controller
25
MD
-
Not used
26
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
27
DPI_P08
-
Not used
28
RESET_MAIN
-
Not used
29
VDD_INT
-
Power supply terminal (+1.1V) (for core)
30
UART_OUT
O
Serial data output to the system controller
31
UART_IN
I
Serial data input from the system controller
32
LED
-
Not used
33, 34
DPI_P12, DPI_P13
-
Not used
35
DAI_P03
-
Not used
36
DPI_P14
-
Not used
37 to 39
VDD_INT
-
Power supply terminal (+1.1V) (for core)
40
SL/SR_IN
I
Audio signal (for surround L-ch/R-ch) input from the digital audio interface receiver
41
SL/SR_OUT
O
Audio signal output terminal Not used
42
BCLK_IN
I
Bit clock signal input from the digital audio interface receiver
43
OPTION_L/
OPTION_R_OUT
O
Audio signal output terminal Not used
44
FRONTHI_L/R_OUT
O
Audio signal output terminal Not used
45
VDD_INT
-
Power supply terminal (+1.1V) (for core)
46
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
47
VDD_INT
-
Power supply terminal (+1.1V) (for core)
48
L/R_OUT
O
Audio signal (for front L-ch/R-ch) output to the stream processor
49
MID/SW2_OUT
O
Audio signal output terminal Not used
50
SBL/SBR_OUT
O
Audio signal output terminal Not used
51
ZONE_L/R
I/O
Not used
52
VDD_INT
-
Power supply terminal (+1.1V) (for core)
53
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
54
MCLK_IN
I
Master clock signal input from the digital audio interface receiver
55
VDD_INT
-
Power supply terminal (+1.1V) (for core)
56
C/SW1_OUT
O
Audio signal (for subwoofer) output to the stream processor and RF modulator
57
A/D_2CH
I
Audio signal input from the digital audio interface receiver
58
C/SW_IN
I
Audio signal (for center and subwoofer) input from the digital audio interface receiver
59
LRCLK_IN
I
L/R sampling clock signal input from the digital audio interface receiver
60
BCLK_OUT
O
Bit clock signal output to the stream processor and RF modulator
HT-CT380/CT381
54
Pin No.
Pin Name
I/O
Description
61
LRCLK_OUT
O
L/R sampling clock signal output to the stream processor and RF modulator
62
SBL/SBR_IN
I
Audio signal (for surround back L-ch/R-ch) input from the digital audio interface receiver
63
L/R_IN
I
Audio signal (for front L-ch/R-ch) input from the digital audio interface receiver
64
VDD_INT
-
Power supply terminal (+1.1V) (for core)
65
DIR_IN
I
Audio signal input from the digital audio interface receiver
66, 67
VDD_INT
-
Power supply terminal (+1.1V) (for core)
68
GND
-
Ground terminal
69
THD_M
O
Thermal detection signal output terminal Not used
70
THD_P
I
Thermal detection signal input terminal Not used
71
VDD_THD
-
Power supply terminal (+3.3V)
72 to 76
VDD_INT
-
Power supply terminal (+1.1V) (for core)
77
FLAG0
O
Interrupt request signal output to the system controller
78, 79
VDD_INT
-
Power supply terminal (+1.1V) (for core)
80
FLAG1
I
Error detection signal input terminal “L”: error
81
FLAG2
I
Audio setting signal input terminal “L”: LPCM audio, “H”: HBR audio
82
FLAG3
-
Not used
83
MLBCLK
-
Not used
84
MLBDAT
-
Not used
85
MLBDO
-
Not used
86
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
87
MLBSIG
-
Not used
88
VDD_INT
-
Power supply terminal (+1.1V) (for core)
89
MLBSO
-
Not used
90
TRST
I
Test reset signal input terminal (for JTAG) Not used
91
EMU
O
Emulation status signal output terminal Not used
92
TDO
O
Test data output terminal (for JTAG) Not used
93
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
94
VDD_INT
-
Power supply terminal (+1.1V) (for core)
95
TDI
I
Test data input terminal (for JTAG) Not used
96
TCK
I
Test clock signal input terminal (for JTAG) Not used
97
VDD_INT
-
Power supply terminal (+1.1V) (for core)
98
RESET
I
Reset signal input from the system controller “L”: reset
99
TMS
I
Test mode selection signal input terminal (for JTAG) Not used
100
VDD_INT
-
Power supply terminal (+1.1V) (for core)
HT-CT380/CT381
55
MAIN BOARD IC3109 SII9535CTUC (HDMI TRANSCEIVER)
Pin No.
Pin Name
I/O
Description
1
SCLK_GPIO9
-
Not used
2
SCK0_IN_GPIO5
-
Not used
3
SD0_IN_SPDIF_IN
-
Not used
4
WS0_IN_GPIO6
-
Not used
5
R0XC–
I
TMDS clock (negative) signal input terminal Not used
6
R0XC+
I
TMDS clock (positive) signal input terminal Not used
7
R0X0–
I
TMDS data (negative) input terminal Not used
8
R0X0+
I
TMDS data (positive) input terminal Not used
9
R0X1–
I
TMDS data (negative) input terminal Not used
10
R0X1+
I
TMDS data (positive) input terminal Not used
11
R0X2–
I
TMDS data (negative) input terminal Not used
12
R0X2+
I
TMDS data (positive) input terminal Not used
13
CVDD10
-
Power supply terminal (+1V)
14
AVDD10
-
Power supply terminal (+1V)
15
AVDD33
-
Power supply terminal (+3.3V)
16
R1XC–
I
TMDS clock (negative) signal input from the HDMI IN 3 connector
17
R1XC+
I
TMDS clock (positive) signal input from the HDMI IN 3 connector
18
R1X0–
I
TMDS data (negative) input from the HDMI IN 3 connector
19
R1X0+
I
TMDS data (positive) input from the HDMI IN 3 connector
20
R1X1–
I
TMDS data (negative) input from the HDMI IN 3 connector
21
R1X1+
I
TMDS data (positive) input from the HDMI IN 3 connector
22
R1X2–
I
TMDS data (negative) input from the HDMI IN 3 connector
23
R1X2+
I
TMDS data (positive) input from the HDMI IN 3 connector
24
R2XC–
I
TMDS clock (negative) signal input from the HDMI IN 1 connector
25
R2XC+
I
TMDS clock (positive) signal input from the HDMI IN 1 connector
26
R2X0–
I
TMDS data (negative) input from the HDMI IN 1 connector
27
R2X0+
I
TMDS data (positive) input from the HDMI IN 1 connector
28
R2X1–
I
TMDS data (negative) input from the HDMI IN 1 connector
29
R2X1+
I
TMDS data (positive) input from the HDMI IN 1 connector
30
R2X2–
I
TMDS data (negative) input from the HDMI IN 1 connector
31
R2X2+
I
TMDS data (positive) input from the HDMI IN 1 connector
32
CVDD10
-
Power supply terminal (+1V)
33
AVDD10
-
Power supply terminal (+1V)
34
AVDD33
-
Power supply terminal (+3.3V)
35
R3XC–
I
TMDS clock (negative) signal input from the HDMI IN 2 connector
36
R3XC+
I
TMDS clock (positive) signal input from the HDMI IN 2 connector
37
R3X0–
I
TMDS data (negative) input from the HDMI IN 2 connector
38
R3X0+
I
TMDS data (positive) input from the HDMI IN 2 connector
39
R3X1–
I
TMDS data (negative) input from the HDMI IN 2 connector
40
R3X1+
I
TMDS data (positive) input from the HDMI IN 2 connector
41
R3X2–
I
TMDS data (negative) input from the HDMI IN 2 connector
42
R3X2+
I
TMDS data (positive) input from the HDMI IN 2 connector
43
RESET_N
I
Reset signal input from the system controller “L”: reset
44
CI2CA_TPWR
I
Not used
45
INT
O
Interrupt signal output to the system controller
46
DSDA0
I/O
Two-way I2C serial data bus terminal Not used
47
DSCL0
I
I2C serial data transfer clock signal input terminal Not used
48
CBUS_HPD0
O
Hot plug detection control signal output terminal Not used
49
R0PWR5V
I
Power supply voltage (+5V) input terminal Not used
50
RSVDH
O
Power supply (+3.3V) output terminal
51
SBVCC5V
-
Power supply terminal (+5V)
52
RSVDL
I
Not used
53
CSCL
I
I2C clock signal input from the system controller
54
CSDA
I/O
Two-way I2C data bus with the system controller
55
DSDA1
I/O
Two-way I2C serial data bus with the HDMI IN 3 connector
56
DSCL1
I
I2C serial data transfer clock signal input from the HDMI IN 3 connector
57
CBUS_HPD1
O
Hot plug detection control signal output to the HDMI IN 3 connector
58
R1PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 3 connector
HT-CT380/CT381
56
Pin No.
Pin Name
I/O
Description
59
DSDA2
I/O
Two-way I2C serial data bus with the HDMI IN 1 connector
60
DSCL2
I
I2C serial data transfer clock signal input from the HDMI IN 1 connector
61
CBUS_HPD2
O
Hot plug detection control signal output to the HDMI IN 1 connector
62
R2PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 1 connector
63
DSDA3
I/O
Two-way I2C serial data bus with the HDMI IN 2 connector
64
DSCL3
I
I2C serial data transfer clock signal input from the HDMI IN 2 connector
65
CBUS_HPD3
O
Hot plug detection control signal output to the HDMI IN 2 connector
66
R3PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 2 connector
67
TXDSDA
I/O
Two-way I2C serial data bus with the ARC HDMI OUT connector
68
TXDSCL
O
I2C serial data transfer clock signal output to the ARC HDMI OUT connector
69
TX_HPD
I
Hot plug detection signal input from the ARC HDMI OUT connector
70
MHL_CD0_GPIO0
-
Not used
71
APLL10
-
Power supply terminal (+1V)
72
XTALVCC33
-
Power supply terminal (+3.3V)
73
XTALOUT
O
System clock output terminal (27 MHz)
74
XTALIN
I
System clock input terminal (27 MHz)
75
XTALGND
-
Ground terminal
76
TPVDD10
-
Power supply terminal (+1V)
77
TXC–
O
TMDS clock (negative) signal output to the ARC HDMI OUT connector
78
TXC+
O
TMDS clock (positive) signal output to the ARC HDMI OUT connector
79
TX0–
O
TMDS data (negative) output to the ARC HDMI OUT connector
80
TX0+
O
TMDS data (positive) output to the ARC HDMI OUT connector
81
TDVDD10
-
Power supply terminal (+1V)
82
TX1–
O
TMDS data (negative) output to the ARC HDMI OUT connector
83
TX1+
O
TMDS data (positive) output to the ARC HDMI OUT connector
84
TX2–
O
TMDS data (negative) output to the ARC HDMI OUT connector
85
TX2+
O
TMDS data (positive) output to the ARC HDMI OUT connector
86
CVDD10
-
Power supply terminal (+1V)
87
ARCRX_TX
I
Digital audio signal input terminal Not used
88
WS0_OUT_DR0_
GPIO7
O
L/R sampling clock signal output to the digital audio interface receiver
89
SCK0_DCK
O
Bit clock signal output to the digital audio interface receiver
90
SD0_0_DL0
O
Digital audio signal output to the digital audio interface receiver
91
MCLK
O
Master clock signal output to the digital audio interface receiver
92
SD0_1_DR1_GPIO1
O
Digital audio signal output to the digital audio interface receiver
93
SD0_2_DL1_GPIO2
O
Digital audio signal output to the digital audio interface receiver
94
SD0_3_DR2_GPIO3
O
Digital audio signal output to the digital audio interface receiver
95
MUTEOUT_GPIO4
O
HDMI muting on/off control signal output terminal “H”: muting on
96
SPDIFOUT_DL2
O
S/PDIF audio signal output to the digital audio interface receiver
97
IOVCC33
-
Power supply terminal (+3.3V)
98
SDO_GPIO10
-
Not used
99
SDI_GPIO11
-
Not used
100
SS_GPIO8
-
Not used
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