Sony HCD-VX8J Service Manual ▷ View online
– 17 –
VIDEO SECTION
Frequency adjustment
1. Connect the frequency counter to check point of the VIDEO
board.
2. Adjust CT503 of the VIDEO board so that the frequency counter
read 27MHz ± 80Hz at STOP condition.
[ VIDEO BOARD ] – SIDE B –
Adjustment Location :
[ VIDEO BOARD ] – SIDE A –
frequency counter
VIDEO board
(29 MHz)
(29 MHz)
+
–
–
SL501
IC502
IC506
(27MHz)
(GND)
SL502
SL503
TEST
MODE
SL501
D502
SL502
CT503
SL503
TEST MODE
VIDEO
FREQUENCY
(27MHz)
(GND)
IC507
IC505
Adjustment Location :
[ BD BOARD ] — SIDE B —
TP
(VC)
(VC)
TP
(RF)
(RF)
TP
(TE)
(TE)
TP
(IOP)
(IOP)
TP
(FE)
(FE)
TP
(AGCCON)
(AGCCON)
– 18 –
SECTION 8
DIAGRAMS
8-1. CIRCUIT BOARDS LOCATION
ENCAPSULATED COMPONENT/TUNER
unit is supplied as the assembled block.
unit is supplied as the assembled block.
MAIN board
PANEL board
CD SW board
SURROUND board
ENCAPSULATED COMPONENT
(EXCEPT THAI)
TUNER unit
(THAI)
(EXCEPT THAI)
TUNER unit
(THAI)
TRANS board
VIDEO board
SENSOR board
CONNECTOR board
BD board
MOTOR (SLIDE) board
MOTOR (TURN) board
AUDIO board
LEAF SW board
HCD-VX8/VX8J
– 19 –
– 20 –
8-2. BLOCK DIAGRAMS
– CD SECTION –
E
F
A
B
C
D
DRIVE
Q101
LD
RF EQ
AMP
SUMMING
AMP
RF
ERROR
AMP
FOCUS
ERROR
AMP
TRACKING
APC LD
AMP
VC
BUFFER
VC
REF
RF AMP
IC103
DIGITAL SERVO
DIGITAL SIGNAL PRCESSOR
IC101
IC381
LASER
DIODE
DETECTOR
OPTICAL PICK-UP BLOCK
(D/Q-Np)
A
C
D
B
E
F
LD
POWER
PD
LD
PD
LD
A
C
D
B
E
F
TE
FE
RFD
RFI
ASYMMETRY
CORRECTION
AUTO
SEQUENCER
SERVO
INTEG-
RATOR
DIGITAL
PLL
EFM
DEMODULATOR
REGISTER
SUB CODE
PROCESSOR
ERROR
CORRECTOR
DATA BUS
32K
RAM
D/A
INTERFACE
DIGITAL
CD DIGITAL
OUT
OPTICAL
OUT
DOUT
SERVO
INTERFACE
DIGITAL
CLV
LD ON
OP AMP
ANALOG SW
A/D
CONVERTER
PWM
GENERATOR
TRACKING
PWM
GENERATOR
FOCUS
PWM
GENERATOR
SLED
PWM
GENERATOR
VC
TRACKING
SERVO
FOCUS
SERVO
SLED
SERVO
SERVO DSP
TFDR
TRDR
FFDR
FRDR
SFDR
SRDR
MDP
DETECTOR
MIRR
DFCT
FOK
D OUT
PCM-D
S STOP
RFDC
FE
TE
CE
VC
SE
CPU
INTERFACE
SENS
DATA
XLAT
CLOK
CLOCK
GENERATOR
XTAI
XTSL
M
M
TRACKING
COIL
FOCUS
COIL
SLED
MOTOR
M102
SPINDLE
MOTOR
M101
T+
T
F+
F
SD+
SD
SP+
SP
FOCUS/TRACKING COIL DRIVE
SPINDLE/SLED MOTOR DRIVE
IC102
VC
TFDR
TRDR
FFDR
FRDR
SFDR
SRDR
XRST
MUTE
09
S101
LIMIT SW
SQCK
A+5V
IC104
XRST
ADATA
BCLK
LRCK
MCK
SENS
CTRL1
DATA
SCLK
SCLK
XLT
CLK
SCOR
SQSO
SCOR
SUBQ
SQCK
LPH
XRST
LD ON
LRCK
BCLK
C2PO
MUTE
MUTE
C2PO
D+5V
MD2
RF AC
ASYI
ASYO
CONTROL SIGNAL
BLOCK
SERVO
BLOCK
VCC
VC
VIDEO
SECTION
• SIGNAL PATH
: CD
: Digital out
: VIDEO
(Page 21)
MAIN
SECTION
(Page 25
M
TABLE
SENSOR
IC702
T. SENS
OPEN
S801
OPEN/CLOSE
DET
OUT1
IN1
IN2
OUT2
M
M701
TURN
TURN
MOTOR
TBL.L
TBL.R
TURN
MOTOR DRIVER
IC701
DISC
SENSOR
IC703
ROTARY
ENCODER
S811
Q701
DISC SENS
ENC 1
ENC 2
ENC 3
ENC 2
ENC 3
M801
SLIDE
MOTOR
OUT2
OUT1
RIN
FIN
SLIDE
MOTOR DRIVER
IC801
LOAD IN
LOAD OUT
A
C
(XTAL 33.8MHz)
4
2
5
7
8
6
11
10
3
4
23
24
27
25
20
22
21
12
13
17
14
16
50
48
49
43
38
41
39
40
42
32
31
34
33
30
29
25
64
63
67
66
14
65
71
3
7
69
15
6
5
4
77
76
8
26
8
8
82
8
8
8
8
8
8
1
12
11
14
13
17
18
15
16
3
2
6
5
INTEG-
RATOR
HCD-VX8/VX8J
– VIDEO SECTION –
– 21 –
– 22 –
SYSTEM
SELECT
S501
65
15
13
09
29
I
2
C.CLK
30
I
2
C.DATA
I
2
C.CLK
I
2
C.DATA
I to U
U to I
TXD
RXD
72
U to I
DSENS
XRESET
TEST LED
NT/PAL
XOUT
+5V
D502
A7
DF LATCH
SHARPNESS
XIN
24
45
BUS
DSP DATA
DSP LATCH
SENSE CLK
DSP CLK
SENSE
DSP MUTE
CTRL1(L:DOUBLE)
CTRL2
LDON
LDON
SCOR
SUBQ DATA
22
34
X501
NTSC
AUTO
PAL
10MHz
X503
27MHz
19
20
X401
8MHz
MECHA. CONTROL
IC502
INTERFACE
IC402
LEVEL SHIFT
IC504
LEVEL SHIFT
IC501
D-RAM
IC507
ROM
IC506
AMP
IC101
OUTPUT AMP
IC401
VIDEO/CD DECODER
IC505
DIGITAL FILTER & D/A CONVERTER
IC509
DATA1O
DATA1I
CLK1
CL680 INT
CL680 INT
CL680 HSEL
CL680 HRDY
680 RESET
DATA0
DATAI
CLK1
INT
INT
HSEL
HRDY
RESET
ADATA
BCLK
LRCK
C2P0
DATA
XLT
CLK
SENS
SCLK
MUTE
CTRL1
LDON
SCOR
SUBQ
SQCK
XRST
MCK
A
CD
SECTION
(Page 20)
11
12
10
13
9
• R CH: Same as L ch
• SIGNAL PATH
: CD
: CHROMA
:Y
: VIDEO
• SIGNAL PATH
: CD
: CHROMA
:Y
: VIDEO
SUBQ CLK
DEVICE RESET
23
19
14
RESET
XIN
XOUT
18
93
73
12
P.ON
38
3
4
5
5
1
2
10
11
27
27
28
18
37
36
77
20
21
21
33
32
31
69
HD-OUT
6
CD-C2P0
CD-LRCK
CD-BCK
HRDY
HD-IN
HCK
HINT
HSEL
RESET
PGIO2/VSYNC/CSYNC
INVERTER
Q502
CD-DATA
MWE
WE
RAS
UCAS
LCAS
A0
A8
DQ1
DQ16
RASO
CAS
MCE
MD0
I
MD15
MA0
I
MA10
C-OUT
Y-OUT
75
DA-DATA
DA-BCK 111
VCK-IN 106
DA-XCLK 86
110
DA-LRCK 108
112
119
117
117
113
114
121
93
60
3
5
5
4
13 14 28 29
38 42
40
10
8
4
13
5
1
1
3
8
12
6
11
1
3
7
5
1
3
19
17
DATA0
CLK1
8
7
10
21 20
4
11
18
MODE
PLM
D/A
CONV
CLOCK
DIVIDER
9
24
1
16 - 19 22 - 26
2 - 10 31 - 39
O0
O7
A11
A17
A0
A10
CE
13 - 15 17 - 21
25 4 28 29 3 2 14 10 12 - 5 27 26 23
58 - 44
10 - 29
22
37
MUTE
Q454
BUFFER
Q301
MUTE
Q453
MIX AMP
Q308,310
BUFFER
Q303,304
TRAP
Q302,306,307
1
3
2
4
14
VIDEO OUT
J302
J301
VIDEO
FREQUENCY
CT503
–5V/IIC DATA
L - CH
R-CH
P. ON/IIC. CLK
XRST
27MHz
384FS
768FS
S VIDEO
OUT
OUT
DATAI
DATAO
CLK1
CLK1
HRDY
INT
HSEL
HSEL
RST
CLK1, DATA0
(XTAL 33.8MHz)
27MHz
RSTB
3.3V REG
Q531
+3.3V
D5V
C
MAIN
SECTION
(Page 25)
E
MAIN
SECTION
(Page 26)
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