Sony HCD-VX880AV Service Manual ▷ View online
57
76
MDATA [15:0]
I/O
Memory address.
77
VSS
—
Ground for core logic and I/O signals.
78
MDATA [15:0]
I/O
Memory address.
79
LDQM
O
SDRAM LDQM.
80
UDQM
O
SDRAM UDQM.
81
VDD
—
3.3-V supply voltage for core logic and I/O signals.
82
MWE
O
SDRAM/EDO write enable. Decoder asserts active LOW to request a write operation
to the SDRAM array.
to the SDRAM array.
83
VSS
—
Ground for core logic and I/O signals.
84
SD-CLK
O
SDRAM system clock.
85
SD-CAS
O
Active LOW SDRAM column address.
86
SD-RAS
O
Active LOW SDRAM row address.
87
VDD
—
3.3-V supply voltage for core logic and I/O signals.
88
SD-CS [1:0]
O
Active LOW SDRAM bank select.
89
VSS
—
Ground for core logic and I/O signals.
90
SD-CS [1:0]
O
Active LOW SDRAM bank select.
91
VDD
—
3.3-V supply voltage for core logic and I/O signals.
92
EDO-CAS
O
Active LOW EDO DRAM column address strobe.
93
VSS
—
Ground for core logic and I/O signals.
94
EDO-RAS
O
Active LOW EDO DRAM row address strobe.
95
VDD
—
3.3-V supply voltage for core logic and I/O signals.
96
MADDR [20:0]
O
Memory address.
97
VSS
—
Ground for core logic and I/O signals.
98 to 100
MADDR [20:0]
O
Memory address.
101
VDD
—
3.3-V supply voltage for core logic and I/O signals.
102
MADDR [20:0]
O
Memory address.
103
VSS
—
Ground for core logic and I/O signals.
104 to 106 MADDR [20:0]
O
Memory address.
107
VDD
—
3.3-V supply voltage for core logic and I/O signals.
108
MADDR [20:0]
O
Memory address.
109
VSS
—
Ground for core logic and I/O signals.
110 to 112 MADDR [20:0]
O
Memory address.
113
VDD
—
3.3-V supply voltage for core logic and I/O signals.
114
MADDR [20:0]
O
Memory address.
115
VSS
—
Ground for core logic and I/O signals.
116
MADDR [20:0]
O
Memory address.
117
VDD
—
3.3-V supply voltage for core logic and I/O signals.
118
MADDR [20:0]
O
Memory address.
119
VSS
—
Ground for core logic and I/O signals.
120 to 122 MADDR [20:0]
O
Memory address.
123
VDD
—
3.3-V supply voltage for core logic and I/O signals.
124
MADDR [20:0]
O
Memory address.
125
VSS
—
Ground for core logic and I/O signals.
126, 127
MADDR [20:0]
O
Memory address.
128
ROM-CS
O
ROM chip select. Open drain signal, must be pulled-up to 3.3 volts.
129
PIO [10:0]
I/O
Programmable I/O pins.
133
PIO [10:0]
I/O
Programmable I/O pins.
134
VDD
—
3.3-V supply voltage for core logic and I/O signals.
136
VSS
—
Ground for core logic and I/O signals.
138
PIO [10:0]
I/O
Programmable I/O pins.
Pin No.
Pin Name
I/O
Function
58
141
PIO [10:0]
I/O
Programmable I/O pins.
142, 143
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
144
VDD
—
3.3-V supply voltage for core logic and I/O signals.
145
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
146
VSS
—
Ground for core logic and I/O signals.
147
PIO [10:0]
I/O
Programmable I/O pins.
148
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
149
VDD
—
3.3-V supply voltage for core logic and I/O signals.
150
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
151
VSS
—
Ground for core logic and I/O signals.
152
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
153
PIO [10:0]
I/O
Programmable I/O pins.
154, 155
VDATA [7:0]
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
157
HSYNC
I/O
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after
the falling (active) edge of HSYNC.
the falling (active) edge of HSYNC.
158
VSYNC
I/O
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the
first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH=Bottom field. VSYNC LOW=Top field)
first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH=Bottom field. VSYNC LOW=Top field)
160
VDD
—
3.3-V supply voltage for core logic and I/O signals.
161
DA-DATA
O
Serial audio samples relative to DA-BCK clock.
162
VSS
—
Ground for core logic and I/O signals.
166
DA-LRCK
O
PCM left-right clock. Identifies the channel for each audio sample. The polarity is
programmable.
167
DA-BCK
O
PCM bit clock. Divided by 8 from DA-XCX, DA-BCK can be either 48 or 32 times the
sampling clock.
168
VDD
—
3.3-V supply voltage for core logic and I/O signals.
169
DA-XCX
I/O
Audio external frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK
can be either 384 or 256 times the sampling frequency.
170
VSS
—
Ground for core logic and I/O signals.
171
DAI-DATA
I
PCM input data, two channels. Serial audio samples relative to DA-BCK clock,
resulting in downmixed audio output.
resulting in downmixed audio output.
172
DAI-LRCK
I
PCM input left-right clock.
173
DAI-BCK
I
PCM input bit clock.
174
PIO [10:0]
I/O
Programmable I/O pins.
175
VDD
—
3.3-V supply voltage for core logic and I/O signals.
176
A-VDD
—
3.3-V analog supply voltage.
177
VCLK
I
Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.
178
SYSCLK
I
System clock. Decoder requires an external 27 MHz TTL oscillator. Drive with the
same 27-MHz as VCK.
same 27-MHz as VCK.
179
A-VSS
—
Analog ground for PLL.
180
CD-DATA
I
Serial CD data.
181
VDD
—
3.3-V supply voltage for core logic and I/O signals.
Pin No.
Pin Name
I/O
Function
59
182
CD-LRCK
I
Programmable polarity 16-bit word synchronization to the decoder
(right channel HIGH).
(right channel HIGH).
183
VSS
—
Ground for core logic and I/O signals.
184
CD-BCK
I
CD bit clock. Decoder accept multiple BCK rates.
185
CD-C2PO
I
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture
on-screen until the next valid picture is decoded.
on-screen until the next valid picture is decoded.
190
PIO [10:0]
I/O
Programmable I/O pins.
193
VDD
—
3.3-V supply voltage for core logic and I/O signals.
195
VSS
—
Ground for core logic and I/O signals.
197
VDD
—
3.3-V supply voltage for core logic and I/O signals.
199
VSS
—
Ground for core logic and I/O signals.
202 to 204 HADDR [2:0]
I
Host address bus. 3-bit address bus selects one of eight host interface registers.
206
CS
I
Host chip select. Host asserts CS to select the decoder for a read or write operation.
The falling edge of this signal triggers the read of write operation.
The falling edge of this signal triggers the read of write operation.
207
R/W
I
Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW to select
write and LOW to select Read.
write and LOW to select Read.
208
RD
I
Read strobe in I mode. Must be held HIGH in M mode.
Pin No.
Pin Name
I/O
Function
60
1
STK-MUTE
O
Power amp ON/OFF signal output
2
POWER
O
Power ON/OFF signal output
3
F-RELAY
O
Front speaker relay control output
4
REAR-RELAY
O
Rear speaker relay control output (Not used)
5
CD-POWER
O
CD power on signal output
6
LINE-MUTE
O
Line mute ON/OFF selection output
7
DBFB-H/L
O
DBFB H/L select signal output
8, 9
–
–
Not used
10
XC-IN
I
11
XC-OUT
O
12
RESET
I
Reset signal input
13
X-OUT
O
X’tal (16MHz)
14
VSS
–
Ground
15
X-IN
I
X’tal (16MHz)
16
VCC
–
Power supply (+5V)
17
NMI
I
Not used (PULL UP EVER+5V)
18
WAKE UP
I
WAKE UP (Fixed at fixed at “L”)
19
SCOR
I
Subcode data request signal output (Not used)
20
RDS-INT
I
21
RDS-DATA
I
22
AC-CUT
I
Back up signal input
23
PL-CLK
O
Clock signal to pro-logic (Not used)
24
PL-DATA
O
Data signal to pro-logic (Not used)
25
PL-LAT
O
Latch signal to pro-logic (Not used)
26
TIMER LED
I
Timer LED ON/OF
27
PROTECTOR
I
Speaker protect ON/OF
28
–
–
Not used
29
IIC-CLK
O
Clock output for IC601
30
IIC-DATA
O
Data output for IC601
31
–
–
Not used
32
SQ-DATA
I
Subcode Q data clock input
33
SQ-CLK
I
Not used
34
SW-MODE
O
Not used
35
CD-DATA
O
CD data output (Not used)
36
RY-SW
I
Head phone swich detect
37
CD-CLK
O
CD clock output (Not used)
38
493-LAT
O
Latch signal output for M62493FP (IC101)
ST-BY LED/
CLOCK-OUT
40
L+R/L-R
I
41
BY-PASS
I
42
FL-SW
I
FL switch ON/OFF
43
STBY RELAY
I
Stand by relay ON/OFF
44
BASS FREQ
O
FREQ high/low signal for SYNC bass
45, 46
–
–
Not used
47
493-DATA
O
Data output for M62493FP (IC101)
48
493-CLK
O
Clock output for M62493FP (IC101)
49
ST-MUTE
O
Tuned mute signal output
• IC501 MASTER CONTROL (M30622MA-A16FP) (MAIN Board (3/4))
Pin No.
Pin Name
I/O
Function
X’tal (32.768MHz)
RDS data interrupt input
39
O
Clock ond stand by LED signal output
Not used
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