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53

Pin No.

Pin Name

I/O

Function

41

TE

I

Tracking error signal input

42

CE

I

Center servo analog input

43

RFDC

I

RF signal input

44

ADI0

O

Test pin (Not used)

45

AVSS0

—

Analog ground

46

IGEN

I

Power supply pin operational amplifiers

47

AVDD

—

Analog power supply

48

ASYO

O

EFM full swing output

49

ASYI

I

Asymmetry comparate voltage input

50

RFAC

I

EFM signal input

51

AVSS1

—

Analog ground

52

CLTV

I

Control voltage input for master VCO

53

FILO

O

Filter output for master PLL

54

FILI

I

Filter input for master PLL

55

PCO

O

Charge-pump output for master PLL

56

AVDD1

—

Analog power supply

57

BIAS

I

Asymmetry circuit constant current input

58

VCTL

I

Control voltage input for variable pitch PLL

59

V16M

I/O

16.9344MHz output (Not used)

60

VPCO

O

Charge-pump output for variable pitch PLL (Not used)

61

DVDD2

—

Digital power supply

62

ASYE

I

Asymmetry circuit ON/OFF

63

MD2

I

Digital-out ON/OFF control

64

DOUT

O

Digital-out output

65

LRCK

O

48-bit slot D/A interface, LR clock output

66

PCMD

O

48-bit slot D/A interface, Serial deta output

67

BCLK

O

48-bit slot D/A interface, bit clock output

68

EMPH

O

Playback disc output in emphasis mode (Not used)

69

XTSL

I

X’tal selection input pin

70

DVSS2

—

Digital ground

71

XTAI

I

X’tal oscillator circuit input

72

XTAO

O

X’tal oscillator circuit output (Not used)

73

SOUT

O

74

SOCK

O

(Not used)

75

XOCT

O

76

SQSO

O

Sub-Q serial output

77

SQCK

I

Clock input for SQSO read-out

78

SCSY

I

Sub-code input

79

SBSO

O

Sub-P through Sub-W serial output (Not used)

80

EXCR

I

Clock input for SBSO read-out

54

1

SENSE

I

Internal status (SENSE) signal input from the CXD3008Q (IC101)

2

SENSE  CLK

O

Sense serial data reading clock signal output to the CXD3008Q (IC101)

3

DSP  DATA

O

Serial data output to the CXD3008Q (IC101)

4

DSP  LATCH

O

Serial data latch pulse output to the CXD3008Q (IC101)

5

DSP  CLK

O

Serial data transfer clock signal output to the CXD3008Q (IC101)

6

LD  ON

O

Laser power selection signal output to the CXA2568M (IC103)    “H”: laser on

7

REMOTE  IN

I

Remote control signal input terminal    Not used (open)

8

BYTE

I

“External data bus line byte selection signal input    “L”: 16 bit, “H”: 8 bit (fixed at “L”)

9

CN  VSS

—

Ground terminal

10

DSP  MUTE

O

Muting on/off control signal output to the CXD3008Q (IC101) “H”: mutin on

11

CTRL1

O

Clock selection signal output to the CXD3008Q (IC101)
“L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz

12

XRESET

I

Reset signal input from the system controller (IC501)  “L”: reset
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”

13

XOUT

O

Main system clock output terminal (10 MHz)

14

VSS

—

Ground terminal

15

XIN

I

Main system clock input terminal (10 MHz)

16

VCC

—

Power supply terminal (+5 V)

17

NMI

I

Non-maskable interrupt input terminal (fixed at “H” in this set)

18

SCOR

I

Subcode sync (S0+S1) detection signal input from the CXD3008Q (IC101)

19

CTRL2

O

AGC  HOLD signal output.

20

8830 HINT

I

Interrupt request signal input from the MPEG video/audio decoder (IC506)

21

NT/PAL  OUT

O

NTSC/PAL select signal output.

22

DF  LATCH

O

Serial data latch pulse output to the D/A converter (IC509)    “L”: activ

23

NC

—

Not used.

24

8830 RESET

O

Reset signal output to the MPEG video/audio decoder (IC506)    “L”: reset

25

JOG1

I

Rotary encoder jog dial pulse input terminal    Not used (fixed at “H”)

26

JOG2

I

Rotary encoder jog dial pulse input terminal    Not used (fixed at “H”)

27

VMUTE

O

Video muting on/off control signal output terminal    “L”: muting on

28

OSD  CS

O

Chip select signal of D/A converter (IC511).

29

I2C/RX

I/O

I

2

C and serial data input from CD mechanism control (IC501).

30

I2C/TX

I/O

I

2

C and serial data output from CD mechanism control (IC501).

31

S-DATA O

O

Serial data output to the MPEG video/audio decoder (IC505) and D/A convertor (IC509)

32

S-DATA I

I

Serial data input from the MPEG video/audio decoder (IC505)

33

S-CLK

O

Serial data transfer clock signal output to the MPEG video/audio decoder (IC505) and D/A
converter (IC509)

34

RTS1

O

RTS signal to serial port (check connector).

35

NC

O

Not used (open)

36

SUBQ  DATA

I

Sub-code Q data input from the CXD3008Q (IC101)

37

SUBQ  CLK

O

Sub-code Q data reading clock signal output to the CXD3008Q (IC101)

38

P. ON

O

Power on/off control signal output terminal    Not used (open)

39

BUS  XRDY

I

Ready signal input terminal    Not used (fixed at “H”)

40

BUS

O

Not used (open)

41

BUS  XHOLD

I

Hold signal input terminal    Not used (fixed at “H”)

Pin No.

Pin Name

I/O

Function

55

Pin No.

Pin Name

I/O

Function

42, 43

BUS

O

Not used (open)

44

BUS  XRD

O

Bus read signal output.

45

BUS

O

Not used.

46

BUS  XWR

O

Bus write signal output.

47

8830-CS

O

Chip select signal output. (IC505)

48

AUDIO  MUTE

O

Audio muting on/off control signal output terminal    “L”: muting on    Not used (open)

49

LOAD  OUT

O

Loading motor drive signal output terminal    Not used (open)

50

LOAD  IN

O

Loading motor drive signal output terminal    Not used (open)

51

INSW

I

Disc detection (load in) switch input terminal    Not used (fixed at “H”)

52

OUTSW

I

Disc detection (load out) switch input terminal    Not used (fixed at “H”)

53

MODEL1

I

Destination setting terminal (fixed at “L”)

54

MODEL2

I

Destination setting terminal (fixed at “L”)

55 to 61

A15 to A9

O

Address signal output for the external device.  Not used

62

VCC

—

Power supply terminal (+5 V)

63

A8

O

Address signal output for the external device.  Not used (open)

64

VSS

—

Ground terminal

65 to 72

A7 to A0

O

Address signal output for the external device.

73

TEST  LED

O

LED drive signal output for the self diagnosis indicator (D502)    Normally: “L” (LED on)

74

TEST1

I

Setting terminal for the test mode 1 (for VCD check)
Normally: fixed at “H” (“L”: test mode)

75

TEST2

I

Setting terminal for the test mode 2 (for SERVO check)
Normally: fixed at “H” (“L”: test mode)

76

TEST3

I

Setting terminal for the test mode 3    Normally: fixed at “H” (“L”: test mode)
Not used (fixed at “H”)

77

DEVICE  RESET

O

System reset signal output to the CXD3008Q (IC101), BA5974FP (IC102) and D/A
converter (IC509)    “L”: reset

78

STANDBY

O

Standby on/off control signal output terminal    Not used (open)

79

FL  CS

O

Chip select signal output terminal    Not used (open)

80

FLBLK

O

Blank control signal output terminal    Not used (open)

81 to 88

D7 to D0

I/O

Two-way data bus with the external device    Not used (open)

89

NC

—

Not used.

90 to 92

KEY1 to KEY3

I

Key input terminal    Not used (fixed at “H”)

93

NT/PAL

I

Video system select switch (S501) input terminal
“L”: PAL, “H”: NTSC, Center voltage: AUTO

94, 95

NC

—

Not used.

96

AVSS

—

Ground terminal (for A/D conversion)

97

NC

—

Not used.

98

VREF

I

Reference voltage (+5 V) input terminal (for A/D conversion)

99

AVCC

—

Power supply terminal (+5 V) (for A/D conversion)

100

NC

—

Not used.

56

1

PIO [10:0]

I/O

Programmable I/O pins.

2 to 4

HDATA [7:0]

I/O

8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0].  MSB of the 32-bit word is written first.  The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

5

VDD

—

3.3-V supply voltage for core logic and I/O signals.

6

HDATA [7:0]

I/O

8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0].  MSB of the 32-bit word is written first.  The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

7

VSS

—

Ground for core logic and I/O signals.

8 to 11

HDATA [7:0]

I/O

8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0].  MSB of the 32-bit word is written first.  The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

12

VDD

—

3.3-V supply voltage for core logic and I/O signals.

13

RESET

I

Hardware reset.  An external device asserts RESET (active LOW) to execute a
decoder hardware reset.  To ensure proper initialization after power in stable, assert
RESET for at least 20 Ms.

14

VSS

—

Ground for core logic and I/O signals.

15

WAIT

O

Active LOW to indicate host initiated transfer is not complete.  WAIT is asserted after
the falling edge of CS and reasserted when decoder is ready to complete transfer cycle.
Open drain signal, must be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.

16

INT

O

Host interrupt.  Open drain signal, must be pulled-up to 3.3 volts.  Driven high for
10 ns before tristate.

17

VDD

—

3.3-V supply voltage for core logic and I/O signals.

19

VSS

—

Ground for core logic and I/O signals.

27

VDD

—

3.3-V supply voltage for core logic and I/O signals.

29

VSS

—

Ground for core logic and I/O signals.

36

VDD

—

3.3-V supply voltage for core logic and I/O signals.

38

VSS

—

Ground for core logic and I/O signals.

40

VDD

—

3.3-V supply voltage for core logic and I/O signals.

42

VSS

—

Ground for core logic and I/O signals.

47

VDD

—

3.3-V supply voltage for core logic and I/O signals.

49

VSS

—

Ground for core logic and I/O signals.

52

PIO [10:0]

I/O

Programmable I/O pins.

53, 54

MDATA [15:0]

I/O

Memory address.

55

VDD

—

3.3-V supply voltage for core logic and I/O signals.

56

MDATA [15:0]

I/O

Memory address.

57

VSS

—

Ground for core logic and I/O signals.

58 to 60

MDATA [15:0]

I/O

Memory address.

61

VDD

—

3.3-V supply voltage for core logic and I/O signals.

62

MDATA [15:0]

I/O

Memory address.

63

VSS

—

Ground for core logic and I/O signals.

64

MDATA [15:0]

I/O

Memory address.

65

VDD

—

3.3-V supply voltage for core logic and I/O signals.

66

MDATA [15:0]

I/O

Memory address.

67

VSS

—

Ground for core logic and I/O signals.

68

MDATA [15:0]

I/O

Memory address.

69

VDD

—

3.3-V supply voltage for core logic and I/O signals.

70

MDATA [15:0]

I/O

Memory address.

71

VSS

—

Ground for core logic and I/O signals.

72 to 74

MDATA [15:0]

I/O

Memory address.

75

VDD

—

3.3-V supply voltage for core logic and I/O signals.

Pin No.

Pin Name

I/O

Function