Sony HCD-VP1 Service Manual ▷ View online
29
29
HCD-VP1
5-15.
SCHEMATIC DIAGRAM – CONTROL Board –
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
no mark : FM
(Page 25)
(Page 25)
30
HCD-VP1
30
5-16.
PRINTED WIRING BOARD – POWER Board –
•
See page 19 for Circuit Boards Location.
• Semiconductor
Location
Ref. No.
Location
D907
C-3
D908
C-3
D909
C-3
D910
D-3
D911
A-2
D912
A-2
D913
A-3
D914
A-3
5-17.
SCHEMATIC DIAGRAM – POWER Board –
The components identified by mark
!
or dotted
line with mark
!
are critical for safety.
Replace only with part number specified.
(Page 26)
(Page 23)
31
• Waveforms
– CD Board –
– CD Board –
1
IC703
!£
(TE) (CD play mode)
2
IC703
!∞
(FE) (CD play mode)
3
IC703
!§
(RFO) (CD play mode)
4
IC701
$∞
(LRCK)
6
IC701
%∞
(RFCK)
7
IC701
^™
(XTAI)
8
IC701
&£
(WFCK)
9
IC701
(§
(MDP) (CD play mode)
430 mVp-p
170 mVp-p
1.3 Vp-p
0.8 Vp-p
22.8
µ
s
5
IC701
$¶
(BCLK)
5.1 Vp-p
470 ns
5.6 Vp-p
136
µ
s
5.2 Vp-p
16.9344 MHz
5.6 Vp-p
136
µ
s
2.6 Vp-p
7.6
µ
s
– MAIN Board –
1
Q357, 358 collector (REC mode)
2
Q360 collector (REC mode)
3
IC801
(£
(TEX)
4
IC801
$º
(XTAL1)
11.6
µ
s
13.6 Vp-p
11.6
µ
s
0.5 Vp-p
32.768 kHz
2.4 Vp-p
4.19 MHz
5.2 Vp-p
32
• IC Block Diagrams
– CD Board –
– CD Board –
IC701
CXD2545Q
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
92
91
90
89
88
87
86
85
84
83
93
94
95
96
97
98
99
100
SLED PWM
GENERATOR
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
PWM GENERATOR
SERVO DSP
FOCUS
SERVO
TRACKING
SERVO
SLED
SERVO
CLV
PROCESSOR
CPU
INTERFACE
NOISE
SHAPER
18-TIMES
OVER SAMPLING
FILTER
CPU
INTERFACE
CPU
INTERFACE
ADDRESS
GENERATOR
CPU
INTERFACE
PRIORITY
ENCODER
CPU
INTERFACE
ERROR
CORRECTOR
CPU
INTERFACE
TIMING
GENERATOR 2
MIRR
DFCT
FOK DETECTOR
32K RAM
RESISTER
D/A
DIGITAL
PROCESSOR
TIMING
GENERATOR 1
SYNC
PROTECTOR
DIGITAL
OUT
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
DIGITAL
PLL
VARI-PITCH
DOUBLE SPEED
CPU
INTERFACE
EFM
DEMODULATOR
SERIAL
PARALLEL
PROCESSOR
CPU
INTERFACE
ASYMMETRY
CORRECTION
1 2 3 4
5 6 7 8 9 10 11
20
19
18
17
16
15
14
13
12
21 22 23
24 25
46
|
50
61 – 51
PEAK
DETECTOR
CLOCK
GENERATOR
MUX
A/D
CONVERTER
SWITCH
&
BUFFER
SERVO
AUTO
SEQUENCER
SERVO
MICRO PROGRAM
INTERFACE
RFC
ADIO
AVSS
IGEN
AVDD
VCKI
VPCO
PDO
TES3
TES2
DVSS
TEST
VCO1
VCO0
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVSS
RFAC
BIAS
ASYI
ASYO
AVDD
ADD
ASYE
PSSL
WDCK
LRCK
XTAI
XTAO
XTSL
DVSS
FSTI
FSTO
D OUT
MD2
C16M
C4M
SCOR
WFCK
EMPH
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
ADD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
4
3
DA01
|
DA11
DA16
|
DA12
26
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