Sony HCD-V919AV / MHC-V919AV Service Manual ▷ View online
VIDEO SECTION
Frequency Adjustment
Connection:
Procedure:
1. Connect the frequency counter to TP508 (27 MHz) on VIDEO
1. Connect the frequency counter to TP508 (27 MHz) on VIDEO
board.
2. Turned power switch on.
3. Press the
3. Press the
[FUNCTION]
button to select the CD.
4. Adjust CT503 on the VIDEO board so that the frequency
counter reading 27.0 MHz ± 80 Hz at stop status.
Adjustment Location:
[VIDEO Board] (Side A)
+
–
–
TP508 (27 MHz)
VIDEO board
frequency counter
IC505
IC507
TP508
(27 MHz)
CT503
VIDEO
Frequency
Adjustment
– 21 –
HCD-V919AV
– 23 –
– 24 –
SECTION 7
DIAGRAMS
7-1.
BLOCK DIAGRAM – SERVO Section –
CD MECHANISM
CONTROLLER
IC502 (1/2)
A/D
CONVERTER
OUT+
OUT–
3
4
7
2
1
5
10
6
4
5
6
16
15
14
13
8
9
19
2
1
77
78
71
55
54
45
47
46
63
20
31
33
34
32
36
38
39
26
93
27
28
29
80
88
89
100
2
4
6
8
10
9
10
4
5
19
20
13
12
27
26
23, 24
A
E
B
C
D
A
A+5V
F
DETECTOR
A
B
C
D
RF
SUMMING
AMP
FOCUS
ERROR AMP
RF EQ
SWITCH
Q102, 103
RF EQ
AMP
TRACKING
ERROR AMP
RFO
17
RFE
FE
FE BIAS
RF AMP,
FOCUS/TRACKING ERROR AMP
IC103
TE
E
F
F I-V AMP
E I-V AMP
AUTOMATIC
POWER
CONTROL
Q101
OPTICAL
TRANSCEIVER
IC391
CD DIGITAL OUT
OPTICAL
APC LD
AMP
APC PD
AMP
LD
LD
PD
LASER DIODE
RFAC
MIX
ASYO
ASYI
CTL1
CTL2
FILTER
FILO
PCO
CLTV
FILI
DIGITAL PLL
ASYMMETRY
CORRECTOR
EFM
DEMODULATOR
REGISTER
DIGITAL SIGNAL PROCESSOR
IC101 (1/2)
MON
MDP
MDS
94 95 96 97
FSW
CLV
PROCESSOR
18-TIMES
OVERSAMPLING
FILTER
NOISE
SHAPER
INTERNAL BUS
32K
RAM
ERROR
CORRECTOR
SUBQ
SQCK
83
SCLK
79
MUTE
76
EXCK
SUBCODE Q
PROCESSOR
SUBCODE P – W
PROCESSOR
SYNC
PROTECTOR
TIMING
GENERATOR 1
TIMING
GENERATOR 2
DATA
DATA
BCK
LRCK
64
XTSL
VCKI
XTAO
62
XTAI
BCLK
LRCK
LRCK
RFCK
GFS
56
C2PO
C2PO
CTL1
DOUT
DIGITAL
OUT
SERIAL/PARALLEL
PROCESSOR
D/A DIGITAL
PROCESSOR
CLOCK
GENERATOR
ADDRESS
GENERATOR
PRIORITY
ENCODER
ENCODER
PEAK
DETECTOR
74
SCOR
73
WFCK
75
SBSO
18
28
SENSE CLK
1
SENSE
5
3
DSP CLK
DSP DATA
4
DSP LATCH
81
SE
TE
FE
RFDC
FOCUS/TRACKING/SLED
SERVO DSP
FOCUS/TRACKING/SLED
PWM GENERATOR
SFDR
IN+
IN–
OUT+
OUT–
IN–
IN+
IN–
IN+
15
MUTE
SRDR
TFDR
TRDR
FFDR
FRDR
SSTP
COUT
S101
(LIMIT)
A+5V
MIRR/DFCT/
FOK
DETECTOR
SERVO AUTO
SEQUENCER
SERVO
INTERFACE
CPU
INTERFACE
CLOK
86
DATA
87
99
XLAT
SENS
FOK
91
92
MIRR
DFCT
IN+, IN–
OUT+
OUT–
M101
(SPINDLE)
MOTOR
DRIVE
XRST
LDON
10
DSP MUTE
MOTOR
DRIVE
COIL
DRIVE
OUT–
OUT+
COIL
DRIVE
M
M
M102
(SLED)
05
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC102
2-AXIS
DEVICE
(TRACKING)
(FOCUS)
DIGITAL SERVO
PROCESSOR
IC101 (2/2)
OPTICAL PICK-UP
(KSS-213D/Q-NP)
LDON
PD
(Page 25)
•
SIGNAL PATH
: CD PLAY
: DIGITAL OUT
I-V AMP
2
1
17
16
2
CTRL1
CTL1
CTL2
11
CTRL2
27
SUBQ DATA
36
SUBQ CLK
SCOR
37
VARI-PITCH
DOUBLE SPEED
MCLK
33.8MHz
B
(Page 25)
DATA, BCK,
LRCK, C2PO
C
(Page 26)
RESET
IC104
D+5V
TBL-L
TBL-R
M
3
6
7
2
MOTOR
DRIVE
DISC TRAY TURN MOTOR DRIVE
IC701
OUT1
OUT2
IN1
IN2
M701
(DISC TRAY TURN)
SYSTEM CONTROLLER
IC501 (1/3)
LEVEL SHIFT
Q701
DISC SENSOR
IC703
DISC TRAY SENSOR
IC702
ROTARY
ENCODER
S811
DISC-SENS
OUT-OPEN
S801
(OPEN/CLOSE DET)
ENC1
ENC2
ENC2
ENC3
75
TBL-SENS 76
4
80
CLOSE
OPEN
81
79
78
2
3
60
61
LOAD-OUT
LOAD-IN
M
10
2
7
4
MOTOR
DRIVE
DISC TRAY SLIDE MOTOR DRIVE
IC801
OUT1
OUT2
FIN
RIN
M801
(DISC TRAY SLIDE)
63
64
HCD-V919AV
– 25 –
– 26 –
7-2.
BLOCK DIAGRAM – AUDIO/ VIDEO CD Section –
PROGRAM ROM
IC506
05
• SIGNAL PATH
: CD PLAY (AUDIO)
: CD PLAY (VIDEO)
D/A
CONVERTER
INPUT
INTERFACE
CIRCUIT
OSC
BUFFER
IC504
LOW-PASS
FILER
IC101
IC101
B.P.F.
B.P.F.
VIDEO
BUFFER
Q301
VIDEO
BUFFER
Q303
VIDEO
BUFFER
Q307
VIDEO
BUFFER
Q308
VIDEO
BUFFER
Q304
VIDEO AMP
IC401 (1/2)
VIDEO AMP
IC401 (2/2)
SHARPNESS
CONTROL SWITCH
Q306
SHARPNESS
FILTER
Q302
VIDEO
MUTE
Q454
VIDEO
MUTE
Q453
Y/C MIX
Q310
BUFFER
Q502
LOW-PASS
FILER
MODE
CONTROL
TIMING CONTROL/
CLOCK GENERATOR
DIGITAL FILTER,
D/A CONVERTER
IC509
MPEG VIDEO/AUDIO DECODER,
VIDEO SIGNAL PROCESSOR
IC505
CD MECHANISM CONTROLLER
IC502 (2/2)
EXPANSION
IC402
14
11
VOUTL
VOUTR
R-CH
10
RSTB
17
18
19
20
21
9
7
24
1
DATA
BCK
LRCK
CD-ROM
INTERFACE
CIRCUIT
MPEG
SYSTEM
DECODER
MPEG
VIDEO
DECODER
VIDEO
PROCESS
CIRCUIT
CPU INTERFACE
AUDIO
INTERFACE
CIRCUIT
MPEG
AUDIO
DECODER
D-RAM/ROM INTERFACE
3
4
5
CD-DATA
C2PO
DATA
BCK
LRCK
DATA, BCK,
LRCK, C2PO
LRCK, C2PO
CD-BCK
CD-LRCK
6
CD-C2PO
MA0 – MA10
MD0 – MD15
D0 – D15
D0 – D15
A0 – A10
A0 – A8
384FSO
768FSO
4
MCKO
X503
27MHz
MD
XT2
XT1
37
14 13
29
28
38 42 40
72
22
19
32
21
20
33
31
12
23
24
60
69
75
113
110
111
108
106
HRDY
Y-OUT
86
DA-XCLK
VCK-IN
DA-DATA
DA-BCK
DA-LRCK
C-OUT
93
114 121
HSEL
112
HD-OUT
119
HD-IN
117
HCK
ML
8
MC
LEVEL
SHIFT
IC501
IC501
B
(Page 24)
DATA, CLK
F
(Page 30)
D
(Page 29)
MCLK
33.8MHz
A
(Page 24)
CD-L
E
(Page 29)
C
(Page 24)
C
Y
DIGITAL
FILTER,
NOISE
SHAPER
CIRCUIT
CIRCUIT
58 – 56, 54, 52 – 50, 48, 46 – 44
10 – 15, 17, 19, 21, 23 – 29
16 – 19, 22 – 26
A0 – A10
12 – 5, 27, 26, 23
D8 – D14
A11 – A17
25, 4, 28, 29, 3, 2, 30
D0 – D7
O0 – O7
A0 – A10
DQ1 – DQ16
ADDRESS BUS
DATA BUS
D-RAM
IC507
A0 – A8
13 – 15, 17 – 21
2 – 5, 7 – 10, 31 – 34, 36 – 39
WE
22
CE
RAS
LCAS
UCAS
CAS
RESET
HINT
CL680 RESET
CL680 HINT
CL680 HRDY
CL680 HRDY
CL680 SEL
DATA1I
93
NT/PAL
TEST LED
CLK1
DATA1O
DATA1O
ITOU
UTOI
45
BUS
DATA
CLK
DF LATCH
34
7
5
SHARPNESS
65
VMUTE
77
XRESET
10
9
18
UTAU
UTAI
29
30
TXD
RXD
29
30
DATA
NEW TYPE
FORMER TYPE
CLK
14 13
12C.CLK
12C.DATA
DATA
CLK
DATA
CLK
XOUT
XIN
11
12
RXD
TXD
RESET
RESET
RAS0
MWE
MCE
DEVICE RESET
RESET
1
3
1
2
3
4
J301
S VIDEO OUT
J302
VIDEO OUT
XOUT
XIN
X501
10MHz
X401
8MHz
NTSC
AUTO
PAL
S501
SYSTEM SELECT
D502
(SELF DIAGNOSIS)
73
13
15
20
19
PGIO2/VSYNC/CSYNC
HCD-V919AV
7-3.
BLOCK DIAGRAM – TAPE DECK Section –
– 27 –
– 28 –
PB EQ AMP
(DECK A)
IC611
PB LEVEL (L)
(DECK A)
REC-L
PB-L
CAPSTAN MOTOR
CONTROL SWITCH
Q1001
CAPSTAN
MOTOR DRIVE
Q336 – 339
1
G
(Page 29)
(Page 30)
L-CH
R-CH
R-CH
HP101
(PLAYBACK)
PB EQ AMP
(DECK B)
IC601
L-CH
R-CH
R-CH
05
R-CH
R-CH
HRPE101 (1/2)
(RECORD/PLAYBACK)
ALC
REC
EQ AMP
AMS
CIRCUIT
DOLBY NR
AMP
CIRCUIT
BIAS
CONTROL
CIRCUIT
DOLBY PASS
R-CH
L.P.F.
BUFFER
Q335
M
M1
(CAPSTAN)
HRPE101 (2/2)
(ERASE)
BIAS OSC
T621
B+
(A+7V)
R-CH
3
46
28
43
36
40
35
34
39
26
31
19 15 16 18 20 22 23 24 25
17
99 94 93 92 90 89 88 87
31
33
32
32
+
48
4
2
RV311
PB LEVEL (L)
(DECK B)
RV301
TAPE SPEED
(NORMAL)
RV1002
TAPE SPEED
(HIGH)
RV1001
REC LEVEL (L)
(DECK B)
RV301
REC BIAS (R)
(DECK B)
RV441
REC BIAS (L)
(DECK B)
BIAS OSC
Q621, 622
REC BIAS
SWITCH
Q623
ROTATION
DETECT SENSOR
(DECK A)
IC1001
RV341
BIAS
TRAP
C331, L331
REC/PB SWITCHING
IC602
SYSTEM CONTROLLER
IC501 (2/3)
DECK PROCESS
DECK A/B SELECT, PB/REC EQ AMP,
DOLBY NR AMP, ALC, AMS
IC301
AIN (L)
BIN (L)
MAOUT
PB OUT (L)
EQ OUT
(L)
MSIN
MSOUT
BIAS ON/OFF
70
120
BIAS (N)
BIAS (C)
BIAS (M)
S1004
A 120/70
B NORM/CROM
ALC ON/OFF
PB A/B
NORM/HIGH
NR ON/OFF
RM ON/OFF
REC/PB/PASS
LM ON/OFF
(DECK A 120/70)
98
S1003
S1001
(DECK A PLAY)
S1002
(DECK B PLAY)
(DECK A HALF)
S1008
(DECK B 120/70)
27
REC OUT (L)
ROUT (L)
RIN (L)
ALC (L)
EQ IN (L)
ALC
IN (L)
44
38
97
AMS-IN
26
A-SHUT
ROTATION
DETECT SENSOR
(DECK B)
IC1002
27
B-SHUT
TRIGGER
PLUNGER DRIVE
(DECK A)
Q333, 334
84
A-TRG
TC-MUTE
R/P-PASS
NR-ON/OFF
REC-MUTE
BIAS
EQ-H/N
PB-A/B
ALC-ON/OFF
TC-RELAY
A-PLAY-SW
B-PLAY-SW
A-HALF
28
S1006
(DECK B HALF)
S1009
(DECK B REC)
S1005
(DECK A REC)
B-HALF
SL1
TRIGGER PLUNGER
DECK A
TRIGGER
PLUNGER DRIVE
(DECK B)
Q331, 332
83
B-TRG
82
17
CAP-M-H/L
CAPM-CNT1P
77
CAPM-CNT2P
CAPSTAN
MOTOR DRIVE
Q340 – 343
85
86
CAPM-CNT1M
CAPM-CNT2M
SL2
TRIGGER PLUNGER
DECK B
95
96
H
• SIGNAL PATH
: PLAYBACK (DECK A)
: PLAYBACK (DECK B)
: RECORD
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