Sony HCD-RG121 / MHC-RG121 Service Manual ▷ View online
41
HCD-RG121
IC371 BU2099FV (MAIN BOARD)
V
SS
N.C.
DATA
CLOCK
LCK
OUTPUT BUFFER (Open Drain)
12BIT SHIFT REGESTER
Q0
Q1
Q2
Q3
Q4
12BIT STORAGE
RAGESTER
RAGESTER
CONTOROL
CIRCUIT
L. P. F
V
DD
OE
SO
Q11
Q10
Q9
Q8
Q7
Q6
Q5
1
2
3
5
6
7
8
4
10
16
15
14
13
12
11
9
17
18
19
20
42
HCD-RG121
5-19. IC PIN FUNCTION DESCRIPTION
• IC101 CXD3058AR (RF AMP) (BD80A BOARD)
Pin No.
Pin Name
I/O
Description
1
MIRR
I/O
Mirror signal input/output (Not used)
2
DFCT
I/O
Defect signal input/output (Not used)
3
FOK
I/O
Focus OK signal input/output (Not used)
4
VSS
–
Internal digital ground
5
LOCK
I/O
GFS is sampled at 460Hz; when GFS is high , this pin outputs a high signal If
GFS is low eight consecutive
6
MDP
O
Spindle motor servo control output
7
SSTP
I
Disk innermost detection signal input
8
IOVSS1
–
I/O digital ground
9
SFDR
O
Sled drive output
10
SRDR
O
Sled drive output
11
TFDR
O
Tracking drive output
12
TRDR
O
Tracking drive output
13
FFDR
O
Focus drive output
14
FRDR
O
Focus drive output
15
IOVDD1
–
I/O digital power supply
16
AVDD0
–
Analog power supply
17
AVSS0
–
Analog ground
18
E
I
E signal input
19
F
I
F signal input
20
TEI
I
Tracking error signal input to DSSP block
21
TEO
O
Tracking error signal output from RF amplifier block
22
FEI
I
Focus error signal input to DSSP block
23
FEO
O
Focus error signal output from RF amplifier block
24
VC
I/O
Center voltage output from RF amplifier block
25
A
I
A signal input
26
B
I
B signal input
27
C
I
C signal input
28
D
I
D signal input
29
AVDD4
–
Analog power supply
30
RFDCO
O
RFDC signal output (Not used)
31
PDSENS
I
Reference voltage pin for PD
32
AC_SUM
O
RFAC summing amplifier output
33
EQ_IN
I
Equalizer circuit input
34
LD
O
APC amplifier output
35
PD
I
APC amplifier input
36
RFC
I
Equalizer cut-off frequency adjustment pin
37
AVSS4
–
Analog ground
38
RFACO
O
RFAC signal output
39
RFACI
I
RFAC signal input or EFM signal input
40
AVDD3
–
Analog power supply
41
BIAS
I
Asymmetry circuit constant current input
42
ASYI
I
Asymmetry comparator voltage input
43
ASYO
O
EFM full-swing output (Low = VSS, High = VDD)
44
VPCO
O
Wide-band EFM PLL charge pump output
45
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
46
AVSS3
–
Analog ground
43
HCD-RG121
Pin No.
Pin Name
I/O
Description
47
CLTV
I
Multiplier VCO1 control voltage input
48
FILO
O
Master PLL (slave = digital PLL) filter output
49
FILI
I
Master PLL filter input
50
PCO
O
Master PLL charge pump output
51
AVDD5
–
Analog power supply
52
DDVROUT
O
DC/DC converter output
53
DDVRSEN
I
DC/DC converter output voltage monitor pin
54
AVSS5
–
Analog ground
55
DDCR
I
DC/DC converter reset pin
56
BCKI
I
D/A interface bit clock input
57
PCMDI
I
D/A interface serial data input (2’s COMP, MSB first)
58
LRCKl
I
D/A interface LR clock input
59
LRCK
O
D/A interface LR clock output f = Fs
60
VSS
–
Internal digital ground
61
PCMD
O
D/A interface serial data output (2’s COMP, MSB first)
62
BCK
O
D/A interface bit clock output
63
VDD
–
Internal digital power supply
64
EMPH
O
High when the playback disc has emphasis, low it has not
65
EMPHI
I
High when de-emphasis is ON, low when input OFF
66
IOVDD2
–
I/O digital power supply
67
DOUT
O
Digital Out output
68
TEST
I
Test pin Normally ground
69
TES1
I
Test pin Normally ground
70
IOVss2
–
I/O digital ground
71
XVSS
–
Master clock ground
72
XTAO
O
Crystal oscillation circuit output
73
XTAI
I
Crystal oscillation circuit input
74
XVDD
–
Master clock power supply
75
AVDD1
–
Analog power supply
76
AOUT1
O
Lch analog output
77
VREFL
O
Lch reference voltage
78
AVSS1
–
Analog ground
79
AVSS2
–
Analog ground
80
VREFR
O
Rch reference voltage
81
AOUT2
O
Rch analog output
82
AVDD2
–
Analog power supply
83
IOVDD0
–
I/O digital power supply
84
RMUT
O
Rch “0” detection flag (Not used)
85
LMUT
O
Lch “0” detection flag (Not used)
86
XTSL
I
Crystal selection input (Not used)
87
IOVSS0
–
I/O digital ground
88
XTACN
I
Oscillation circuit control Self-oscillation when high, oscillation stop when low
89
SQSO
O
Subcode Q 80-bit and PCM peak and level data output, CD TEXT data output
90
SQCK
I
SQSO readout clock input
91
SBSO
O
Subcode P to W serial output
92
EXCK
I
SBSO readout clock input
93
XRST
I
System reset Reset when low
94
SYSM
I
Mute input Muted when high
95
D ATA
I
Serial data input from CPU
96
VSS
–
Internal digital ground
44
HCD-RG121
Pin No.
Pin Name
I/O
Description
97
XLAT
I
Latch input from CPU The serial data is latched at the falling edge
98
CLOCK
I
Serial data transfer clock input from CPU
99
VDD
–
Internal digital power supply
100
SENS
O
SENS output to CPU
101
SCLK
I
SENS serial data readout clock input
102
ATSK
I/O
Anti-shock input/output
103
WFCK
O
WFCK output (Not used)
104
XUGF
O
XUGF output (Not used)
105
XPCK
O
XPCK output (Not used)
106
GFS
O
GFS output (Not used)
107
C2PO
O
C2PO output (Not used)
108
SCOR
O
High output when the subcode sync, S0 or S1, is detected
109
VDD
–
Internal digital power supply
110
C4M
O
4 2336MHz output (Not used)
111
WDCK
O
Word clock output f = 2Fs (Not used)
112
COUT
I/O
Track number count signal input/output (Not used)
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