Sony HCD-NXM2D Service Manual ▷ View online
69
HCD-NXM2D
1, 2
D5, D6
I/O
Two-way data bus with CXP973064-245R
3
VSS
—
Ground
4
D7
I/O
Two-way data bus with CXP973064-245R
5
A0
I
Address signal input from CXP973064-245R
6
VDD
—
Power supply (+3.3V)
7
A1
I
Address signal input from CXP973064-245R
8
VDD5V
—
Power supply (+5V)
9 to 14
A2 to A7
I
Address signal input from CXP973064-245R
15
VSS
—
Ground
16
XWAIT
O
Not used
17
XRD
I
Read strobe signal input from CXP973064-245R
18
XWR
I
Write strobe signal input from CXP973064-245R
19
XCS
I
Chip select signal input from CXP973064-245R
20, 21
XINT0, XINT1
O
Interrupt signal output to CXP973064-245R
22
VDD
—
Power supply (+3.3V)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to ZIVA5X-C2F
25
VSS
—
Ground
26
HDB8
O
Error flag signal output to ZIVA5X-C2F
27
HDB6
O
Stream data signal output to ZIVA5X-C2F
28
VDDS
—
Power supply (+5V)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to ZIVA5X-C2F
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to ZIVA5X-C2F
33
VSS
—
Ground
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to ZIVA5X-C2F
36
VDD
—
Power supply (+3.3V)
37
HDBC
O
Not used
38
VDDS
—
Power supply (+5V)
39
HDB2
O
Stream data signal output to ZIVA5X-C2F
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to ZIVA5X-C2F
42
VSS
—
Ground
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to ZIVA5X-C2F
45
HDBF
O
Not used
46
XSAK
O
Serial data effect flag signal output to ZIVA5X-C2F
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XDCK
O
Serial data transfer clock signal output to ZIVA5X-C2F
49
XSHD
O
Header flag signal (Not used)
50
VDD
—
Power supply (+3.3V)
51
REDY
O
Not used
52
VSS
—
Ground
53
XHAC
I
DVD mode: Serial data request signal input from ZIVA5X-C2F
54
HINT
O
Not used (Pull up)
55
XS16
O
Not used (Pull up)
56
HA1
I
Not used (Pull up)
57
XPDI
I/O
Not used (Pull up)
Pin No.
Pin Name
I/O
Description
• IC701 TMC57929PGF-RDP (DVD DECODER) (DBM07 Board)
70
HCD-NXM2D
Pin No.
Pin Name
I/O
Description
58
VDDS
—
Power supply (+5V)
59, 60
HA0, HA2
I
Not used (Pull up)
61
VSS
—
Ground (open)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply (+3.3V)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply (+3.3V)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply (+3.3V)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground
91
MA9/MNT0
O
Address signal output to the D-RAM
92
MNT1/MNT1
O
EEPROM ready signal output to CXP973064-245R
93
MNT2/MNT2
O
Address signal output to the D-RAM (not used)
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply (+3.3V)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply (+5V)
104 to 106
MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to CXP973064-245R
108
VSS
—
Ground
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply (+3.3V)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal
117
RFIN
I
RF signal input from the DVD/CD RF amplifier
118, 119
VCCA5, VCCA4
—
Power supply (+3.3V)
120
VCOR1
—
VCO oscillating range setting resistor connected
121
VCOIN
I
VCO input
122, 123
GNDA4, GNDA3
—
Ground
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
71
HCD-NXM2D
Pin No.
Pin Name
I/O
Description
128, 129
VCCA3, VCCA2
—
Power supply (+3.3V)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134
GNDA2, GNDA1
—
Ground
135
SPO
O
Spindle motor control signal output to FAN8035L
136
VC2
I
Middle point voltage (+1.65V) input
137
MDIN2
I
Spindle motor servo drive signal input
138
MDIN1
I
MDP input
139
VCCA1
—
Power supply (+3.3V)
140
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
141
VSS
—
Ground
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply (+3.3V)
144
MDPOUT
O
Phase error output of internal CLV circuit
145
DEFECT
I
Defect signal input (Not used)
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from CXD3068Q
147
EXCK
O
Subcode serial data reading clock signal output to CXD3068Q
148
SBIN
I
Subcode serial data input from CXD3068Q
149
VSS
—
Ground
150
SCOR
I
Subcode sync (S0+S1) detection signal input from CXD3068Q
151
WFCK
I
Write frame clock signal input from CXD3068Q
152
VDD5V
—
Power supply (+5V)
153
XRCI
I
Not used (Pull down)
154
VDDS
—
Power supply (+5V)
155
C2PO
I
C2 pointer signal input from CXD3068Q
156
VDD
—
Power supply (+3.3V)
157
DBCK
O
Bit clock signal (2.8224 MHz) output (Not used)
158
BCLK
I
Bit clock signal (2.8224 MHz) input from CXD3068Q
159
DDAT
O
PCM data (Not used)
160
MDAT
I
Serial data input from CXD3068Q
161
VSS
—
Ground
162
DLRC
O
L/R sampling clock signal (Not used)
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from CXD3068Q
164
XRST
I
Reset signal input from CXP973064-245R “L”: reset
165
IFS0
I
Not used (connected to ground)
166
IFS1
I
Not used (connected to VDD)
167
XTAL
I
33.8688 MHz clock signal input from SM8707GV
168
VSS
—
Ground
169
XTA2
O
System clock output (33.8688 MHz)
170
XTA1
I
System clock input (33.8688 MHz)
171
VDD
—
Power supply (+3.3V)
172 to 176
D0 to D4
I/O
Two-way data bus with the CXP973064-245R
72
HCD-NXM2D
Pin No.
Pin Name
I/O
Description
• IC901 CXP973064-245R (MECHANISM CONTROLLER) (DBM07 Board)
1
NO_USE
O
Not used (open)
2
SDEN
O
Serial data enable signal output to SP3723CAFOPM
3
DOCTRL/
O
Digital out on/off control signal output to CXD3068Q
ISBTEST
4
XRST_2753
O
Not used
5
SDA_EEP
I/O
Data bus with the EEPROM
6
MNT1
I
EEPROM ready signal input from TMC57929PGF-RDP
7
FCS_JMP_1
O
Focus jump 1 signal output to the FAN8035L
8
FCS_JMP_2
O
Focus jump 2 signal output to the FAN8035L
9
SENS_CD
I
Internal status (SENSE) signal input from CXD3068Q
10
CDSP2
O
Not used
11
CDSP4
O
Not used
12
XCS_DVD
O
Chip select signal output to TMC57929PGF-RDP
13
VSS
—
Ground
14 to 21
D0 to D7
I/O
Two-way data bus with TMC57929PGF-RDP
22
INIT0_DVD
I
Interrupt signal input from TMC57929PGF-RDP
23
INIT1_DVD
I
Interrupt signal input from TMC57929PGF-RDP
24
MSCK_SAMBA
O
Not used
25
XRST_1882
O
Reset signal output to TMC57929PGF-RDP
26
SCOR
I
Subcode sync (S0+S1) detection signal input from CXD3068Q
27
LAT_CD
O
Serial data latch pulse signal output to CXD3068Q
28
LD ON
O
Laser diode on/off control signal output to SP3723CAFOPM
29
MIRR
I
Mirror signal input from SP3723CAFOPM
30
COUT_CD
I
Numbers of track counted signal input from SP3723CAFOPM
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS_ZIVA
O
Chip select signal output to ZIVA5X-C1F
33
SI_ZIVA
I
Serial data input from ZIVA5X-C1F
34
SO_ZIVA
O
Serial data output to ZIVA5X-C1F
35
SCK_ZIVA
O
Serial data transfer clock signal output to ZIVA5X-C1F
36
DRVIRQ
O
Interrupt request signal output to ZIVA5X-C1F
37
DRVRDY
O
Ready signal output to ZIVA5X-C1F
38
RST
I
System reset signal input from ZIVA5X-C1F
39
VSS
—
Ground
40
XTAL
I
System clock input terminal (20 MHz)
41
EXTAL
O
System clock output terminal (20 MHz)
42
VDD
—
Power supply (+3.3V)
43, 44
SLED_A, SLED_B
O
Sled motor drive signal output to FAN8035L
45
SCK_DSD
O
Clock output to TMC57929PGF-RDP
46
SDOUT_DSD
O
Serial data output (Not used)
47
SDIN_DSD
I
Serial data input (Not used)
48
READY_DSD
I
Ready signal input (Not used)
49
DATA_CD
O
Serial data output to CXD3068Q
50
CLOK_CD
O
Serial data transfer clock signal output to CXD3068Q
51
XMSLAT
O
Serial data latch pulse signal (Not used)
52
SQSO
I
Subcode Q data input from TMC57929PGF-RDP
53
MUTE_DSD
O
Muting on/off control signal (Not used)
54
SQCK
O
Subcode Q data reading clock signal output to TMC57929PGF-RDP
55
VSS
—
Ground
56
CONTROL_2
I
Not used
Click on the first or last page to see other HCD-NXM2D service manuals if exist.