Sony HCD-NXM2D Service Manual ▷ View online
65
HCD-NXM2D
• IC Pin Function Descriptions
• IC207 ZIVA5X-C2F (DVD SYSTEM PROCESSOR) (DMB07 BOARD)
Pin No.
Pin Name
I/O
Description
1
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
2
HA1
I/O
Address bus
3 to 11
HD15 to HD7
I/O
Data bus (address signal multiplexed)
12
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
13
GNDP
—
Ground terminal (I/O signal)
14 to 19
HD6 to HD1
I/O
Data bus (address signal multiplexed)
20
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
21
GNDP
—
Ground terminal (I/O signal)
22
HD0
I/O
Data bus (address signal multiplexed)
23
HDTACK
I/O
Acknowledge signal input/output for host data transfer (not used)
24
HIRQ0
I
Interrupt signal input for Medusa (not used)
25
WEH.UDS
I/O
Host upper data strobe signal output (not used)
26
WEL.LDS
I/O
Host lower data strobe signal output (not used)
27
HREAD
I/O
Read/write strobe signal output (not used)
28
GPIO0
I/O
Jig detection port (pull-up)
29
GND
—
Ground terminal (inside core)
30
VDD
—
Power supply terminal (+1.8V) (inside core)
31
GND25
—
Ground terminal (SDRAM I/O signal)
32
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
33 to 42
MA9 to MA0
O
SDRAM address bus
43
GND25
—
Ground terminal (SDRAM I/O signal)
44
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
45, 46
MA10,MA11
O
SDRAM address bus
47
BA1
O
SDRAM bank select 1 signal output
48
BA0
O
SDRAM bank select 0 signal output
49
MCS0
O
SDRAM chip select 0 signal output
50
MCS1
O
Not used
51
MRAS
O
SDRAM row address strobe signal output
52
MCAS
O
SDRAM column address strobe signal output
53
MWE
O
SDRAM write enable signal output (“H” : read, “L” : write)
54
GND25
—
Ground terminal (SDRAM I/O signal)
55
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
56
MCLK
O
SDRAM Clock output
57 to 60
MD0 to MD3
I/O
SDRAM data
61
GND25
—
Ground terminal (SDRAM I/O signal)
62
MDQM0
O
Byte read /write mask signal 0 output
63
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
64 to 71
MD6 to MD11
I/O
SDRAM data
72
GND25
—
Ground terminal (SDRAM I/O signal)
73
MDQM1
O
Byte read /write mask signal 1 output
74
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
75 to 78
MD12 to MD15
I/O
SDRAM data
79
GND
—
Ground terminal (inside core)
80
VDD
—
Power supply terminal (+1.8V) (inside core)
81 to 84
MD16 to MD19
I/O
SDRAM data
85
GND25
—
Ground terminal (SDRAM I/O signal)
86
MDQM2
O
Byte read /write mask signal 2 output
87
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
66
HCD-NXM2D
88 to 95
MD20 to MD27
I/O
SDRAM data
96
GND25
—
Ground terminal (SDRAM I/O signal)
97
MDQM3
O
Byte read /write mask signal 3 output
98
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
99 to 102
MD28 to MD31
I/O
SDRAM data
103
GND25
—
Ground terminal (SDRAM I/O signal)
104
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
105
VCLK
I/O
System clock (not used)
106
XCK_I/O_SEL
I/O
5.1ch/downmix switch signal output (not used)
107
VS
O
S1 signal output
108
I/P SW
O
Progressive/interlace switch signal output
109
CDSEL
O
CD-DA selection signal output
110
MREQ
O
Audio muting request signal output
111
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
112
GNDP
—
Ground terminal (I/O signal)
113
MDI
O
Serial data output to the D/A converter
114
MC
O
Serial data clock output to the D/A converter
115
ML
O
Latch enable signal output to the D/A converter
116
HIRQ2_
I
Busy signal input from the EEPROM
117
VDAC_4B
—
Video DAC bias bit 4 (connected to the ground)
118
VDAC_VDD4
—
Power supply terminal (+3.3V) (Video DAC 4)
119
VDAC_4
O
VDAC output 4
120
VDAC_3B
—
Video DAC bias bit 3 (connected to the ground)
121
VDAC_VDD3
—
Power supply terminal (+3.3V) (Video DAC 3)
122
VDAC_3
O
VDAC output 3
123
VDAC_2B
—
Video DAC bias bit 2 (connected to the ground)
124
VDAC_VDD2
—
Power supply terminal (+3.3V) (Video DAC 2)
125
VDAC_2
O
VDAC output 2
126
VDAC_1B
—
Video DAC bias bit 1 (connected to the ground)
127
VDAC_VDD1
—
Power supply terminal (+3.3V) (Video DAC 1)
128
VDAC_1
O
VDAC output 1
129
VDAC_0B
—
Video DAC bias bit 0 (connected to the ground)
130
VDAC_VDD0
—
Power supply terminal (+3.3V) (Video DAC 0)
131
VDAC_0
O
VDAC output 0
132
VDAC_DVSS
—
Ground terminal (Video DAC digital system)
133
VDAC_DVDD
—
Power supply terminal (+3.3V) (Video DAC digital system)
134
VDAC_REFVDD
—
Power supply terminal (Video DAC reference)
135
VDAC_REF
I
Reference voltage input terminal(for Video DAC)
136
VDAC_REFVSS
—
Ground terminal (Video DAC reference)
137
XVSS
—
Ground terminal (crystal oscillator)
138
XOUT
O
Crystal oscillation signal output (not used)
139
XIN
I
Crystal oscillation signal input
140
XVDD
—
Power supply terminal (crystal oscillator)
141
AVSS2
—
Ground terminal (analog PLL)
142
AVDD2
—
Power supply terminal (+3.3V) (analog PLL)
143
AVDD1
—
Power supply terminal (+3.3V) (analog PLL)
144
AVSS1
—
Ground terminal (analog PLL)
145
VDD
—
Power supply terminal (+1.8V) (inside core)
146
GND
—
Ground terminal (inside core)
147
XCK
O
Audio system clock output
Pin No.
Pin Name
I/O
Description
67
HCD-NXM2D
Pin No.
Pin Name
I/O
Description
148
LRCK
O
LRCK signal output for audio
149
BCK
O
BCK signal output for audio
150
DATA0(DM)
O
Audio data(Down Mix signal) output (not used)
151
DATA1(FLR)
O
Audio data(Front L/R signal) output
152
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
153
GNDP
—
Ground terminal (I/O signal)
154
DATA2(SLR)
O
Audio data(Rear L/R signal) output
155
DATA3(CSW)
O
Audio data(Center/Subwoofer signal) output
156
IEC958
O
S/PDIF signal
157
DAI_DATA
I
Data input from ADC (not used)
158
DAI_BCK
I
BCK signal input from ADC (not used)
159
DAI_LRCK
I
LRCK signal input from ADC (not used)
160
I2C_CL
I/O
I2C clock bus
161
I2C_DA
I/O
I2C data bus
162
CS(ZIVA_E2P)
O
Chip select signal output to the EEPROM
163
RXD1
I
Serial data input for check jig
164
TXD1
O
Serial data output for check jig
165
WRITE_CTRL(ZIVA_E2P)
O
Write control signal output to the EEPROM
166
GNDP
—
Ground terminal (I/O signal)
167
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
168
SDDATA7
I
SDBus data7 input
169
SDDATA6
I
SDBus data6 input
170
SDDATA5
I
SDBus data5 input
171
SDDATA4
I
SDBus data4 input
172
GND
—
Ground terminal (inside core)
173
VDD
—
Power supply terminal (+1.8V) (inside core)
174
SDDATA3
I
SDBus data3 input
175
SDDATA2
I
SDBus data2 input
176
SDDATA1
I
SDBus data1 input
177
SDDATA0
I
SDBus data0 input
178
SDREQ
O
SDBus data request signal output
179
SDEN
I
SDBus data enable signal input
180
GNDP
—
Ground terminal (I/O signal)
181
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
182
SDERROR
I
SDBus data error signal input
183
SDCLK
I
SDBus data clock input
184
HIRQ1
I
Interrupt signal input from the mechanism controller
185
DRVCLK
I
Serial data clock input from the mechanism controller
186
DRVTX
I
Serial data input from the mechanism controller and the EEPROM
187
DRVRX
I
Serial data output to the mechanism controller and the EEPROM
188
DRVRDY
O
Ready signal input from the mechanism controller
189
VNW
—
Power supply for 5V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux
191
RST_SPC
O
Reset signal output to the mechanism controller
192
INT/EXT
O
Input selection signal output for SDBus or ADC (not used)
193
HCS2
O
Chip select signal output for Medusa (not used)
194
HCS1
I/O
Not used
195
HCS0
O
Chip select signal output to the external ROM
196
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
197
TRST
I
Reset signal input
68
HCD-NXM2D
Pin No.
Pin Name
I/O
Description
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset input
203
BUS CLK
I/O
Not used
204
GND
—
Ground terminal (inside core)
205
VDD
—
Power supply terminal (+1.8V) (inside core)
206
HA3
I/O
Address bus 3
207
HA2
I/O
Address bus 2
208
GNDP
—
Ground terminal (I/O signal)
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