Sony HCD-MD595 Service Manual ▷ View online
82
• BD (MD) BOARD IC151 CXD2662R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output terminal “H” is output when focus is on (“L”: NG)
Not used (open)
Not used (open)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC1001)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC1001)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC1001)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC1001)
6
SCLK
I (S)
Serial data transfer clock signal input from the MD mechanism controller (IC1001)
7
XLAT
I (S)
Serial data latch pulse signal input from the MD mechanism controller (IC1001)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC1001)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC1001)
10
XRST
I (S)
Reset signal input from the MD mechanism controller (IC1001) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC1001)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller
(IC1001) “L” is output every 13.3 msec Almost all, “H” is output
(IC1001) “L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD mechanism controller (IC1001)
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the MD mechanism controller (IC1001)
15
TX
O
Magnetic head on/off signal output to the over write head drive (IC181)
16
OSCI
I
System clock signal (90.3168 MHz) input terminal
17
OSCO
O
System clock signal (512Fs=90.3168 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 90.3168 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 90.3168 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode Not used
20
DIN1
I
Digital audio signal input terminal when recording mode
21
DOUT
O
Digital audio signal output terminal when playback mode
22
DADTAI
I
Recording data input from the A/D converter (IC1005)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the D/A converter (IC1006), A/D converter
(IC1005)
(IC1005)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input from the D/A converter (IC1006), A/D converter (IC1005)
25
ADDT
I
Recording data input terminal Not used (fixed at “L”)
26
DADT
O
Playback data output terminal Not used (open)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
28
XBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
29
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM (IC152)
35
A10
O
Address signal output to the D-RAM (IC152)
36 to 40
A04 to A08
O
Address signal output to the D-RAM (IC152)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC152) “L” active
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
83
Pin No.
Pin Name
I/O
Description
44
XCAS
O
Column address strobe signal output to the D-RAM (IC152) “L” active
45
A09
O
Address signal output to the D-RAM (IC152)
46
XRAS
O
Row address strobe signal output to the D-RAM (IC152) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC152) “L” active
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC101)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC101)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC101)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC101)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC101)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
TEST4
I
Input terminal for the test Not used (fixed at “H”)
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC101)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC101)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC101)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC101)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
TEST0
O
Input terminal for the test Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC141)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC141)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC141)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Two-way data bus with the D-RAM (IC152)
84
Pin No.
Pin Name
I/O
Description
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC141)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC141)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC141)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC141)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC141)
95
FGIN
I (S)
96
TEST1
I
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Input terminal for the test (fixed at “L”)
85
• MD DIGITAL BOARD IC1001 M30805SGP (MD MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
—
O
Not used (open)
3
LVL1
O
L-ch level output terminal Not used (open)
4
LVL0
O
R-ch level output terminal Not used (open)
5 to 7
—
O
Not used (open)
8
MUTE
O
Muting control signal output to the D/A converter (IC1006) “L”: muting
9
DARST
O
Reset signal output to the D/A converter (IC1006) “H”: reset
10
SLICERSEL
O
IEC958 input selection signal output to the D/A converter (IC1006) “L”: MD, “H”: CD
11
LD-LOW
O
Loading motor drive voltage control signal output for the loading motor driver (IC1004)
“H” active
“H” active
12
LDIN
O
Motor control signal output to the loading motor driver (IC1004) “L” active *1
13
LDOUT
O
Motor control signal output to the loading motor driver (IC1004) “L” active *1
Laser modulation select signal output to the HF module switch circuit
Stop: “L”, Playback power: “H”,
Recording power:
14
MOD
O
15
BYTE
I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
16
CNVSS
I
Mode setting terminal “H”: processor mode (fixed at “H”)
17
X-CIN
I
Sub system clock input terminal Not used (open)
18
X-COUT
O
Sub system clock output terminal Not used (open)
19
RESET
I
System reset signal input from the reset signal generator (IC931) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
20
XOUT
O
Main system clock output terminal (10 MHz)
21
VSS0
—
Ground terminal
22
XIN
I
Main system clock input terminal (10 MHz)
23
VCC0
—
Power supply terminal (+3.3V)
24
NMI
I
Non-maskable interrupt input terminal “L” active (fixed at “H” in this set)
25
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
26
P.DOWN
I
Power down detection signal input from the system controller (IC501)
“L”: power down, normally: “H”
“L”: power down, normally: “H”
27
SQSY
I
Subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
28
NC
O
Not used (open)
29
LDON
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
30
LIMIT-IN
I
Detection input from the sled limit-in detect switch (S101)
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
2 sec
0.5 sec
*1 Loading motor (M103) control
Mode
Terminal
LDIN (pin qs)
“L”
“H”
“L”
“H”
LDOUT (pin qd)
“H”
“L”
“L”
“H”
LOADING
EJECT
BRAKE
RUN IDLE
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