DOWNLOAD Sony HCD-MD595 Service Manual ↓ Size: 7.16 MB | Pages: 108 in PDF or view online for FREE

Model
HCD-MD595
Pages
108
Size
7.16 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-md595.pdf
Date

Sony HCD-MD595 Service Manual ▷ View online

49
Checking Location:
IC171
IC101
TP
(VC)
TP
(FE)
TP (TE)
TP (RF)
– BD (CD) BOARD (Conductor Side) –
51
51
HCD-MD595
F
C
B
D
A
E
I
J
J
I
B
A
C
D
E
F
DETECTOR
1
2
J
I
4
5
6
7
A
B
C
D
8
9
E
F
LD
PD
LASER DIODE
ILCC
PD
OPTICAL PICK-UP BLOCK
(KMS-262A/J1N)
AUTOMATIC
POWER
CONTROL
Q121, 122
LASER ON
SWITCH
Q101
OVER WRITE
HEAD DRIVE
IC181, Q181, 182
11
10
APC
PD
LD/PD
AMP
APCREF
I-V
AMP
I-V
AMP
AT
AMP
B.P.F.
29
30
WBL
ADFM
ADIN
32
ADFG
ABCD
AMP
FOCUS
ERROR AMP
TRACKING
ERROR AMP
35
34
26
28
ABCD
FE
TE
SE
V-I
CONVERTER
20
F0CNT
WBL
3T
EQ
SERIAL/
PARALLEL
CONVERTER,
DECODER
COMMAND
17
16
18
SWDT
SCLK
XLAT
RF AMP
B.P.F.
46
RFO
40
RF AGC
& EQ
AGCI
EQ
38
RF
RF AMP,
FOCUS/TRACKING ERROR AMP
IC101
TEMP
48 47
MORFO
MORFI
3T
PEAK &
BOTTOM
WBL
33
AUX
63
37
PEAK
36
BOTM
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC141
6
8
OUT4F
OUT4R
M
M101
(SPINDLE)
27
25
OUT2F
OUT2R
M
M102
(SLED)
21
23
OUT1F
OUT1R
12
10
OUT3F
OUT3R
FCS+
FCS–
TRK+
TRK–
2-AXIS
DEVICE
(TRACKING)
(FOCUS)
3
4
IN4R
IN4F
29
30
IN2F
IN2R
19
18
IN1F
IN1R
14
15
IN3F
IN3R
MOD
SPFD
SPRD
92
91
88
89
86
85
APCREF
SFDR
SRDR
FFDR
FRDR
TFDR
TRDR
16
PSB
PWM GENERATOR
AUTOMATIC
POWER
CONTROL
DIGITAL
SERVO
SIGNAL
PROCESS
75
66
65
67
ANALOG MUX
A/D CONVERTER
AUTO
SEQUENCER
FROM CPU
INTERFACE
DIGITAL SERVO
SIGNAL PROCESSOR
IC151 (2/2)
RECP
AUX1
ABCD
FE
TE
SE
PEAK
BOTM
81
80
82
XLRF
CKRF
DTRF
XLAT
SCLK
SWDT
PLL
FILTER
60
59
62
61
FILI
PCO
CLTV
FILO
100
EFMO
25
ADDT
22
DATAI
15
TX
53
54
57
ASYO
ASYI
RFI
SCTX
HR901
OVER WRITE HEAD
ADIP
DEMODULATOR/
DECODER
78
ADFG
SPINDLE
SERVO
F0CNT
94 93
SPFD
SPRD
SUBCODE
PROCESSOR
SAMPLING
RATE
CONVERTER
DIGITAL
AUDIO
INTERFACE
DIN0
DOUT
DIGITAL SIGNAL PROCESSOR,
EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER
IC151 (1/2)
DADT
INTERNAL BUS
CLOCK
GENERATOR
XBCK
LRCK
FS256
OSCI
OSCO
CPU
INTERFACE
MONITOR
CONTROL
10
XRST
12
DQSY
11
SQSY
14
XINT
9 8
5 6 7
SENS
SRDT
SWDT
SCLK
XLAT
1
2
3
4
MNT0
MNT1
MNT2
MNT3
SHOCK
XBUSY
SWDT
SCLK
XLAT
47
38 42 50
58 56
MNT1 (SHOCK)
MNT2 (XBUSY)
DIG-RST
SQSY
DQSY
LDON
WRPWR
MOD
XINT
SENS
SRDT
12
13
LDIN
LDOUT
5
6
05
2
10
4
M
IN1
IN2
OUT1 OUT2
VREF
LOADING
MOTOR DRIVE
IC1004
REFERENCE
VOLTAGE SWITCH
Q1001, 1002
M103
(LOADING)
49, 48, 50, 51
2, 3, 24, 25
DQ1 – DQ4
34 – 31, 36 – 40, 35
9 – 12, 15 – 19, 21, 8
A0 – A10
D0 – D3
A00 – A10
43
22
47
4
46
5
44
23
XOE
XWE
XRAS
XCAS
OE
WE
RAS
CAS
D-RAM
IC152
DIN1
MD MECHANISM CONTROLLER
IC1001 (1/2)
74
13
64
14
79
83
12
HF MODULE
16
17
DADTI
DOUT
A
(Page 52)
LRCK, BCK
DIN0
B
(Page 52)
C
(Page 52)
D
(Page 52)
27 32 48 40
25
29
OP-LEVEL
133
35
REFLECT
PROTECT
LD-LOW
M+7V
11
EEP-WP
60
SCL
66
SDA
61
30
43
LIMIT-IN
REC-SW
S101
(LIMIT IN)
51
OUT-SW
 SIGNAL PATH
: MD PLAY
: MD REC
: CD PLAY
COMPA-
RATOR
EFM/ACIRC
ENCODER/DECODER
SHOCK PROOF
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
26
S105
(REC POSITION)
S103
(PACK OUT)
PLAY-SW 49
S104
(PLAY POSITION)
28
21
20
19
29
27
24
XBCKI
23
LRCKI
68
67
S102-1
(REFLECT RATE DETECT)
S102-2
(PROTECT DETECT)
–1
S102
S104
S103
S105
S101
–2
BCK
LRCK
X171
90.3168MHz
EEPROM
IC195
7
6
5
WP
SCL
SDA
COMPARATOR
IC102
HF MODULE
SWITCH
Q131 – 134
ON: When the over write head is
        recording position
ON: When the optical pick-up is
       inner position  
ON: When the eject slider is
       open position
ON: When the eject slider is
       playback position
ON: When the high reflection
       rate disc detect
ON: When the REC-proof claw is
        close (un-protect)
SECTION  6
DIAGRAMS
6-1.
BLOCK  DIAGRAM  – MD SERVO Section –
HCD-MD595
52
52
6-2.
BLOCK  DIAGRAMS  – D/A, A/D CONVERTER Section –
7
30
8
15
93
8
26
17
11
12
34
91
13
19
18
53
52
22
32
31
90
89
39
38
5
3
115
36
37
22
69
54
55
16
15
RESET SWITCH
Q1103
MOTOR
DRIVE
CLOSE
OPEN
S1
CD TRAY OPEN/CLOSE
DETECT
5
6
2
10
LOADING
MOTOR DRIVE
IC1102
M
M
M201
(LOADING)
DIGITAL SIGNAL
SELECT SWITCH
IC1008
OPTICAL
RECEIVER
IC121
DIGITAL
OPTICAL IN
IEC958
DECODER
MUTING
Q1103, 1104
DATA IN/OUT
INTERFACE
DIGITAL
INTERFACE
DECIMATION
FILTER
CLOCK AND
TIMING CIRCUIT
AUDIO FEATURE
PROCESSOR
INTERPOLATOR
NOISE SHAPER
D/A
CONVERTER
BLOCK
12
13
29
18
22
1
CD MECHANISM CONTROLLER
IC1101
DC-
CANCELLATION
FILTER
A/D
CONVERTER
BLOCK
11
12
33
37
116
9
118
10
124
13
21
1
3
8
7
CLOCK CONTROL
A/D CONVERTER
IC1005
122 
 199, 113 
 102
100 
 94, 92, 85 
 77, 73
25 
 18, 8 
 1, 48, 17, 16
29, 31, 33, 35, 38, 40, 42, 44,
30, 32, 34, 36, 39, 41, 43, 45
63
65
90
26
28
11
14
20
19
RESET SIGNAL
GENERATOR
IC941
RESET SWITCH
Q931
B.UP +3.3V
B
(Page 51)
C
(Page 51)
D
(Page 51)
A
(Page 51)
E
(Page 54)
F
(Page 53)
G
(Page 53)
H
(Page 53)
K
(Page 54)
D/A CONVERTER
IC1006
MD MECHANISM
CONTROLLER
IC1001 (2/2)
FLASH
MEMORY
IC1002
R-CH
R-CH
X101
16MHz
DATA
CLK
SUBQ
SQCLK
XLT
SENSE
SCOR
LDON
X4
CTRL1
SPINDLE MUTE
BDRST
BDPWR
X1
X2
CD-DATA
CD-CLK
SQDATA
SQCK
X-LAT
SENS
SCOR
LDON
X1 – X4
X1 – X2
SPDL MUTE
RST
DOUT
AMUTE
AC-OUT
RESET
IN-SW
OUT-SW
I2CHELP
I2CHELP
I2CCLK
I2CDAT
LOD-POS
LOD-NEG
FIN
RIN
OUT1
OUT2
SPDIF1
SPDIF0
SLICER-
SEL
SLSEL
OPTSEL
LOCK
LOCK
MUTE
I2SBCKOUT
I2SLRCKOUT
BCK
WS
CLKOUT
VOUTL
VOUTR
RESET
BCK
LRCK
DAT AO
VINL
VINR
SCLK
PWON
IICDATA
IICCLK
IICHELP
OPTSEL
SLSEL
LOCK
MUTE
P.DOWN
I2CBUSY
I2CCLK
I2CDAT
XIN
CS0
OE
WE
WP
XOUT
RESET
OE
WE
WP
CE
DALOCK
DARST
ADPDWN
SLICERSEL
OPTSEL
D0 
 D15
DQ0 
 DQ15
A0 
 A18
A0 
 A18
X1001
10MHz
 SIGNAL PATH
 R-ch is omitted due to same as L-ch.
: CD PLAY
: MD PLAY
: MD REC
: OPTICAL IN
LIN
LOUT
P.DOWN
DADTI
BCK, LRCK
DOUT
DIN0
BDPWR
IICDATA, IICCLK
IICHELP
05
CD BLOCK
(BU-21BD53)
OP ASSY
(A-MAX. 2)
53
53
HCD-MD595
6-3.
BLOCK  DIAGRAM  – MAIN Section –
AM
L
R
TAPE IN
ANALOG
IN
J602
J101 (1/2)
R-CH
R-CH
R-CH
27
36
38
37
39
26
28
25
24
23
95
96
2
4
14
13
16
22
RDS SIGNAL
BUFFER
Q401
RDS DECODER
IC401
X401
4.332MHz
35
36
X502
32.768MHz
39
38
X501
16MHz
INPUT
SELECT
SWITCH
TONE
CONTROL
CIRCUIT
VOLUME
CONTROL
CIRCUIT
BASS BOOST
CONTROL
CIRCUIT
35
REC
25
27
28
29
21 22 20
1 2 100
30
CPU INTERFACE
SYSTEM CONTROLLER
IC501 (1/2)
 SIGNAL PATH
 R-ch is omitted due to same as L-ch.
: FM
: CD PLAY
: MD REC
: TAPE IN (PLAY)
: TAPE OUT (REC)
: ANALOG IN
F
18
3
5
VREF
R-CH
D881
INPUT SELECT SWITCH,
TONE CONTROL,
ELECTRICAL VOLUME
IC301
44
32
43
POWER AMP
IC801
DC DETECT
Q871
MUTING
Q801
MUTING
Q841
OVER LOAD
DETECT
Q802
PROTECT
DETECT
Q872, 873
MUTING
CONTROL
Q552
MUTING
CONTROL
Q551
D802
+
+
26
R-CH
R-CH
+
R-CH
THERMAL
DETECT
Q874, 875
TH801
+
+
R-CH
L
R
SPEAKER
IMPEDANCE
USE 6-16
TM881
L
R
TAPE OUT
PHONES
J101 (2/2)
R-CH
RELAY DRIVE
Q881
45
48 67
R-CH
R-CH
R-CH
G
(Page 52)
MUTING
Q101
MUTING
CONTROL
Q102
J601
PC LINC
CN104
CN102
H
(Page 52)
(Page 52)
BUFFER
Q112
BUFFER
Q111
3
6
2
7
BUFFER
BUFFER
IIC BUS EXTENDER
IC103
POWER
DATA
CLK
DATA
CLK
TAPE
CONTROL
05
TUNER PACK
FM ANT
GND
AM ANT
GND
L
R
DOUT
DIN
CLK
CE
TUNED
STEREO
MUTE
FM DET OUT
MUX
RDAT
RCLK
XO
XI
ST->TA DATA
TA->ST DATA
ST CLK
ST CE
ST TUNED
ST STEREO
RDS DATA
RDS CLK
ST MUTE
92
GEQ DATA
GEQ CLK
GEQ CE
XTIN
XTOUT
XIN
XOUT
IIC HELP
IIC DATA
IIC CLK
PC POWER
SX
SY
LX
LY
STK MUTE
PROTECT
LINE MUTE
SPK RELAY
REC MUTE
HEADPHONE IN
DATA
CLK
LAT
B-O
LINE
TC
CDMD
ST
T-O
V-I
V-O
B-I
OUT
LOUT
IIC DATA, IIC CLK,
IIC HELP
IIC HELP
IIC DATA
IIC CLK
LIN
6
1
1
5
5
COAXIAL
FM 75
(AEP, UK)
Q301
FEED BACK
SWITCH
Q103
FAN MOTOR
SWITCH
M901
(FAN)
D101
M+7V
63
FAN
M
M
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