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– 87 –

•

Pin No.

Pin Name

I/O

Function

1

MNT0 (FOK)

O

Focus OK signal output to the MD mechanism controller (IC316)                                                     
“H” is output when focus is on (“L”: NG)

2

MNT1 (SHCK)

O

Track jump detection signal output to the MD mechanism controller (IC316)

3

MNT2 (XBUSY)

O

Busy signal output to the MD mechanism controller (IC316)

4

MNT3 (SLOC)

O

Spindle servo lock status monitor signal output to the MD mechanism controller (IC316)

5

SWDT

I

Writing serial data signal input from the MD mechanism controller (IC316)

6

SCLK

I

Serial data transfer clock signal input from the MD mechanism controller (IC316)

7

XLAT

I

Serial data latch pulse signal input from the MD mechanism controller (IC316)

8

SRDT

O (3)

Reading serial data signal output to the MD mechanism controller (IC316)

9

SENS

O (3)

Internal status (SENSE) output to the MD mechanism controller (IC316)

10

XRST

I

Reset signal input from the MD mechanism controller (IC316)    “L”: reset

11

SQSY

O

Subcode Q sync (SCOR) output to the MD mechanism controller (IC316)                                        
“L” is output every 13.3 msec     Almost all, “H” is output

12

DQSY

O

Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller 
(IC316)    “L” is output every 13.3 msec     Almost all, “H” is output

13

RECP

I

Laser power selection signal input from the MD mechanism controller (IC316)                                
“H”: recording mode, “L”: playback mode

14

XINT

O

Interrupt status output to the MD mechanism controller (IC316)

15

TX

I

Recording data output enable signal input from the MD mechanism controller (IC316)              
Writing data transmission timing input (Also serves as the magnetic head on/off output)

16

OSCI

I

System clock signal (512Fs=22.5792 MHz) input terminal

17

OSCO

O

System clock signal (512Fs=22.5792 MHz) output terminal

18

XTSL

I

Input terminal for the system clock frequency setting                                                                         
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)

19

RVDD

—

Power supply terminal (+3.3V) (digital system)

20

RVSS

—

Ground terminal (digital system)

21

DIN

I

Digital audio signal input terminal when recording mode (for digital in)

22

DOUT

O

Digital audio signal output terminal when playback mode (for digital out)    Not used

23

ADDT

I

Recording data input from the A/D, D/A converter (IC201)

24

DADT

O

Playback data output to the A/D, D/A converter (IC201)

25

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)

26

XBCK

O

Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201)

27

FS256

O

Clock signal (11.2896 MHz) output to the A/D, D/A converter (IC201)

28

DVDD

—

Power supply terminal (+3.3V) (digital system)

29 to 32

A03 to A00

O

Address signal output to the D-RAM (IC124)

33

A10

O

Address signal output to the external D-RAM    Not used (open)

34 to 38

A04 to A08

O

Address signal output to the D-RAM (IC124)

39

A11

O

Address signal output to the external D-RAM    Not used (open)

40

DVSS

—

Ground terminal (digital system)

41

XOE

O

Output enable signal output to the D-RAM (IC124)    “L” active

42

XCAS

O

Column address strobe signal output to the D-RAM (IC124)    “L” active

43

A09

O

Address signal output to the D-RAM (IC124)

44

XRAS

O

Row address strobe signal output to the D-RAM (IC124)    “L” active

45

XWE

O

Write enable signal output to the D-RAM (IC124)    “L” active

46

D1

I/O

Two-way data bus with the D-RAM (IC124)

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 88 –

Pin No.

Pin Name

I/O

Function

47

D0

I/O

48

D2

I/O

Two-way data bus with the D-RAM (IC124)

49

D3

I/O

50

MVCI

I

Digital in PLL oscillation input from the external VCO    Not used (fixed at “L”)

51

ASYO

O

Playback EFM full-swing output terminal

52

ASYI

I (A)

Playback EFM asymmetry comparator voltage input terminal

53

AVDD

—

Power supply terminal (+3.3V) (analog system)

54

BIAS

I (A)

Playback EFM asymmetry circuit constant current input terminal

55

RFI

I (A)

Playback EFM RF signal input from the CXA2523AR (IC101)

56

AVSS

—

Ground terminal (analog system)

57

PDO

O (3)

Phase comparison output for clock playback analog PLL of the playback EFM    Not used (open)

58

PCO

O (3)

Phase comparison output for master clock of the recording/playback EFM master PLL

59

FILI

I (A)

Filter input for master clock of the recording/playback master PLL

60

FILO

O (A)

Filter output for master clock of the recording/playback master PLL

61

CLTV

I (A)

Internal VCO control voltage input of the recording/playback master PLL

62

PEAK

I (A)

Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)

63

BOTM

I (A)

Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)

64

ABCD

I (A)

Light amount signal (ABCD) input from the CXA2523AR (IC101)

65

FE

I (A)

Focus error signal input from the CXA2523AR (IC101)

66

AUX1

I (A)

Auxiliary signal (I

3

 signal/temperature signal) input from the CXA2523AR (IC101)

67

VC

I (A)

Middle point voltage (+1.65V) input from the CXA2523AR (IC101)

68

ADIO

O (A)

Monitor output of the A/D converter input signal    Not used (open)

69

AVDD

—

Power supply terminal (+3.3V) (analog system)

70

ADRT

I (A)

A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)

71

ADRB

I (A)

A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)

72

AVSS

—

Ground terminal (analog system)

73

SE

I (A)

Sled error signal input from the CXA2523AR (IC101)

74

TE

I (A)

Tracking error signal input from the CXA2523AR (IC101)

75

AUX2

I (A)

Auxiliary signal input terminal    Not used (fixed at “H”)

76

DCHG

I (A)

Connected to the +3.3V power supply

77

APC

I (A)

Error signal input for the laser automatic power control    Not used (fixed at “H”)

78

ADFG

I

ADIP duplex FM signal (22.05 kHz 

±

 1 kHz) input from the CXA2523AR (IC101)

79

F0CNT

O

Filter f0 control signal output to the CXA2523AR (IC101)

80

XLRF

O

Serial data latch pulse signal output to the CXA2523AR (IC101)

81

CKRF

O

Serial data transfer clock signal output to the CXA2523AR (IC101)

82

DTRF

O

Writing serial data output to the CXA2523AR (IC101)

83

APCREF

O

Control signal output to the reference voltage generator circuit for the laser automatic power 
control

84

LDDR

O

PWM signal output for the laser automatic power control    Not used (open)

85

TRDR

O

Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)

86

TFDR

O

Tracking servo drive PWM signal (+) output to the BH6511FS (IC152)

87

DVDD

—

Power supply terminal (+3.3V) (digital system)

88

FFDR

O

Focus servo drive PWM signal (+) output to the BH6511FS (IC152)

89

FRDR

O

Focus servo drive PWM signal (–) output to the BH6511FS (IC152)

90

FS4

O

Clock signal (176.4 kHz) output terminal (X’tal system)    Not used (open)

91

SRDR

O

Sled servo drive PWM signal (–) output to the BH6511FS (IC152)

92

SFDR

O

Sled servo drive PWM signal (+) output to the BH6511FS (IC152)

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 89 –

Pin No.

Pin Name

I/O

Function

93

SPRD

O

Spindle servo drive PWM signal (–) output to the BH6511FS (IC152)

94

SPFD

O

Spindle servo drive PWM signal (+) output to the BH6511FS (IC152)

95

FGIN

I

96

TEST1

I

97

TEST2

I

98

TEST3

I

99

DVSS

—

Ground terminal (digital system)

100

EFMO

O

EFM signal output terminal when recording mode

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

Input terminal for the test (fixed at “L”)

– 90 –

•

Pin No.

Pin Name

I/O

Function

1

JOG0

I

Rotary encoder jog dial pulse input terminal    Not used (fixed at “H”)

2

JOG1

I

Rotary encoder jog dial pulse input terminal    Not used (fixed at “H”)

3

DAOUT0

O

Monitor output terminal for the test    C1 error rate is output when test mode

4

DAOUT1

O

Monitor output terminal for the test    ADER is output when test mode

5

SQSY

I

Subcode Q sync (SCOR) input from the CXD2652AR (IC121)
“L” is input every 13.3 msec    Almost all, “H” is input

6

REMCON

I

Remote control signal input terminal    Not used (fixed at “H”)

7

EMP

O

Emphasis control signal output to the A/D, D/A converter (IC201)

8

BYTE

I

External data bus line byte selection signal input    “L”: 16 bit, “H”: 8 bit (fixed at “L”)

9

CNVSS

—

Ground terminal

10

XT-IN

I

Sub system clock input terminal    Not used (fixed at “L”)

11

XT-OUT

O

Sub system clock output terminal    Not used (pull down)

12

SYSTEM-RST

I

System reset signal input from the reset signal generator (IC706) and master controller (IC707)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

13

XOUT

O

Main system clock output terminal (7 MHz)

14

GND

—

Ground terminal

15

XIN

I

Main system clock input terminal (7 MHz)

16

+3.3V

—

Power supply terminal (+3.3V)

17

NMI

I

Non-maskable interrupt input terminal (fixed at “H” in this set)

18

AMUTE

O

Audio line muting on/off control signal output terminal    “L”: line muting on
 Not used (pull down)

19

PWR-DWN

I

Power down detection signal input terminal    “L”: power down, normally: “H”

20

DQSY

I

Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2652AR (IC121)
“L” is input every 13.3 msec    Almost all, “H” is input

21

STB

O

Strobe signal output to the power supply circuit    “H”: power on, “L”: standby mode
Not used (pull down)

22

DARST

O

Reset signal output terminal    “L”: reset    Not used (pull down)

23

XINT

I

Interrupt status input from the CXD2652AR (IC121)

24

DA-EN

O

Enable signal output to the A/D, D/A converter (IC201) (for D/A converter block)
“L”: enable

25

AD-EN

O

Enable signal output to the A/D, D/A converter (IC201) (for A/D converter block)
“L”: enable

26

MEC-BUSY

O

MD mechanism controller busy status monitor output to the master controller (IC707)

27

FLCS

O

Chip select signal output terminal    Not used (pull down)

28

FLCLK

O

Display serial data transfer clock signal output terminal    Not used (pull down)

29

—

I

Not used (fixed at “L”)

30

FLDATA

O

Display serial data output terminal    Not used (pull down)

31

TXD

O

UART communication data output to the master controller (IC707)

32

RXD

I

UART communication data input from the master controller (IC707)

33

CLK

I

Serial clock signal input from the master controller (IC707)

34

MAS-BUSY

I

Master controller busy status monitor input from the master controller (IC707)

35

SWDT

O

Writing data output to the CXD2652AR (IC121)

36

SRDT

I

Reading data input from the CXD2652AR (IC121)

37

SCLK

O

Serial clock signal output to the CXD2652AR (IC121)

38

XLAT

O

Serial data latch pulse signal output to the CXD2652AR (IC121)

39

—

I

Not used (fixed at “L”)

40

DIG-RST

O

Reset signal output to the CXD2652AR (IC121) and BH6511FS (IC152)    “L”: reset