Sony HCD-MD1DX / HCD-MD1EX Service Manual ▷ View online
– 83 –
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
100 99 98 97 96 95
94 93
EFMO
DVSS
TEST3
TEST2
TEST1
FGIN
SPFD
SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
55 RFI
56 AVSS
54 BIAS
53 AVDD
52 ASYI
51 ASYO
67 VC
66 AUX1
65 FE
64 ABCD
63 BOTM
62 PEAK
50
MVCI
49
D3
48
D2
47
D0
46
D1
45
XWE
44
XRAS
43
A09
42
XCAS
41
XOE
40
DVSS
39
A11
38
A08
37
A07
36
A06
35
A05
34
A04
33
A10
32
A00
31
A01
30
A02
29
A03
28
DVDD
26
XBCK
27
FS256
25
LRCK
24
DADT
23
ADDT
22
DOUT
21
DIN
20
DVSS
19
NC
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
CONTROL
SPINDLE
SERVO
EACH
BLOCK
BLOCK
EACH
BLOCK
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
ADIP
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
IC121
CXD2652AR
IC152
BH6511FS-E2
– 84 –
– MAIN Board –
IC702
LB1641
IC153
LB1830M-S-TE-L
IC201
AK4520A-VF-E2
IC706
M62016L
1
LOGIC
PREDRIVER
VREF
2
3
4
5
10
9
8
7
6
IN2
IN1
VM
VREF
VCONT
VCC
OUT2
GND
OUT1 VS
∆Σ
MODULATOR
8
×
INTERPOLATOR
COMMON
VOLTAGE
CLOCK
DIVIDER
SERIAL I/O
INTERFACE
LPF
∆Σ
MODULATOR
∆Σ
MODULATOR
∆Σ
MODULATOR
8
×
INTERPOLATOR
DECIMATION
FILTER
DECIMATION
FILTER
LPF
16
15
17
18
19
20
21
22
23
24
25
26
27
28
1 2
3
4
5 6
7
8
9 10
14
13
12
11
VCOM
AOUTR
AOUTL
CMODE
PWAD
PWDA
DGND
VD
TST1
TST2
TST3
DEM1
DEM0
MCLK
SDTO
SDTI
SCLK
LRCK
DIF1
DIF0
AGND
VA
AINL–
AINL+
AINR–
VREFH
AINR+
VREFL
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
– 85 –
– PANEL Board –
IC901
M66004M8FP
IC710
BU1922-E2 (AEP, UK)
QUALITY BIT
GENERATOR
DEFFERENTIAL
DECODER
BIPHASE
SYMBOL
SYMBOL
DECODER
OSCILLATOR
AND
DIVIDER
57kHz
BANDPASS
(8th ORDER)
CONTAS LOOP
VARIABLE AND
FIXED DIVIDER
FIXED DIVIDER
REFERENCE
VOLTAGE
ANTI-
ALIASING
FILTER
CLOCKED
COMPARATOR
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
RECONSTRUCTION
FILTER
14
15
16
13
12
11
10
9
3
2
1
4
5
6
7
8
CLOCK REGENERATION
AND SYNC
VP1
RDCL
TS7
OSCO
OSCI
V
DDD
V
SSD
TEST
TSTL
D
QUAL
RDDA
Vref
MUX
V
DDA
V
SSA
CIN
SCOUT
INDICATION
CODE
RESISTOR
(8BIT x 16)
DECODER
(35BIT x 16)
DECODER
(35BIT x 16)
CODE/COMMAND
CONTROL
CIRCUIT
INDICATION
CONTROL
RESISTOR
INDICATION
CONTROLLER
DIGITAL
OUTPUT
CIRCUIT
OUTPUT
CIRCUIT
CODE
WRITE
SERIAL
RECEIVE
CIRCUIT
OUTPUT
PORT
(2BIT)
CLOCK
GENERATOR
CIRCUIT
RAM WRITE
CODE SELECT
DIG12
|
DIG15
V
CC
2
SEG0
|
SEG26
V
SS
XIN
XOUT
V
CC
1
RES
DIG11
|
DIG0
CS
CLK
DATA
SEG35
|
SEG27
P1
P0
14
15
16
17
18
19
20
21
22
23
|
31
13
1
|
12
SEGMENT OUTPUT CIRCUIT
59
|
33
60
32
VP
64
|
61
– 86 –
7-24.
IC PIN FUNCTION DESCRIPTION
•
BD (MD) BOARD IC101 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Function
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2652AR (IC121)
17
SCLK
I
Serial data transfer clock signal input from the CXD2652AR (IC121)
18
XLAT
I
Serial data latch pulse signal input from the CXD2652AR (IC121)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
from the CXD2652AR (IC121)
from the CXD2652AR (IC121)
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2652AR (IC121)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2652AR (IC121)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2652AR (IC121)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2652AR (IC121)
34
FE
O
Focus error signal output to the CXD2652AR (IC121)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2652AR (IC121)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC121)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC121)
38
RF
O
Playback EFM RF signal output to the CXD2652AR (IC121)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
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