Sony HCD-M700 Service Manual ▷ View online
97
97
HCD-M700
6-38. Printed Wiring Board – POWER Board –
• See page 54 for Circuit Boards Location.
E
E
E
(Page 84)
(Page 74)
FH913
FH914
F906
FH911
FH912
F907
IC904
IC903
IC902
IC901
FH907
F904
FH908
FH909
FH910
T902
F903
JW923
JW924
D907
D906
D909
JW922
JW911
D915
D914
D908
C903
D903
D904
C902
D902
JW921
D905
C905
CN902
C904
D921
JW910
JR905
D920
C928
D919
R904
R915
D923
JW909
C927
R914
C921
C918
R903
C920
C933
Q906
Q907
Q905
CN904
JW901
JW903
JW902
C926
D917
D916
C925
C931
C924
C939
C935
C932
C919
JW904
CN903
C934
Q902
R901
JW908
JW907
R906
R913
R912
D918
D912
D913
R905
C901
RY901
JW915
D926
C923
C922
Q904
D925
JW905
R909
C937
L902
L903
LF901
CN901
D910
D911
D924
R908
JW906
C930
C936
C938
JW916
CLP901
JW918
F901
FH903
FH904
S901
JW920
JW917
T901
C929
L901
Ref. No.
Location
D902
D-4
D903
D-4
D904
D-5
D905
D-5
D906
E-4
D907
E-4
D908
E-5
D909
E-5
D910
B-5
D911
B-5
D912
B-5
D913
B-5
D914
E-6
D915
E-6
D916
E-7
D917
E-7
D918
C-5
D919
D-5
D920
D-5
D921
D-5
D923
D-6
D924
B-6
D925
B-6
D926
C-6
IC901
B-6
IC902
B-6
IC903
C-6
IC904
E-5
Q902
C-5
Q904
C-6
Q905
D-6
Q906
D-6
Q907
D-6
• Semiconductor
Location
98
98
HCD-M700
6-39. IC Pin Function Description
• IC101 CXA2523AR RF Amplifier (BD Board)
• IC101 CXA2523AR RF Amplifier (BD Board)
Pin No.
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
Pin Name
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
Description
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2662R
Serial clock input from the CXD2662R
Latch signal input from the CXD2662R “L”: Latch
Stand by signal input “L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2662R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2662R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2662R
FM signal output of ADIP
ADIP signal comparator input ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2662R
I3 signal/temperature signal output to the CXD2662R
(Switching with a serial command)
Focus error signal output to the CXD2662R
Light amount signal output to the CXD2662R
RF/ABCD bottom hold signal output to the CXD2662R
RF/ABCD peak hold signal output to the CXD2662R
RF equalizer output to the CXD2662R
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD Board)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
48
49
50, 51
52
53
54
55
56
57
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
O
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
Pin Name
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
Description
Function FOK signal output to the system control (monitor output)
“H” is output when focus is on (Not used)
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output) (Not used)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control “L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system control
Laser power switching input from the system control “H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input) (Fixed at “L”)
Digital audio output (Optical output) (Open)
Serial data input (Fixed at “L”)
LR clock input “H” : Lch, “L” : R ch (Fixed at “L”)
Serial data clock input (Fixed at “L”)
Data input from the A/D converter
Data output to the D/A converter (Not used)
LR clock output for the A/D and D/A converter (44.1 kHz) (Not used)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
99
HCD-M700
Pin No.
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96 to 98
99
100
I/O
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
I (S)
I
—
O
Pin Name
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
Description
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523AR (22.05
±
1 kHz)
Filter f0 control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
100
HCD-M700
• IC103 MB91307APFV-G-BND-E1 DVD System Controller (DVD Board)
Pin No.
Pin Name
I/O
Description
1 to 5
HA17 to HA21
O
Address signal output
6
HA22
—
Not used
7
WP
O
Write control signal output to the EEPROM
8
TRM/XKRCS
—
Not used
9
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
10
AVRH
—
Reference voltage input (+3.3V) terminal (for A/D converter)
11
AVSS
—
Ground terminal (for A/D converter)
12
AN0
I
Mode 0 set input terminal
13
AN1
I
Mode 1 set input terminal
14
AN2
I
Mode 2 set input terminal
15
AN3
I
Mode 3 set input terminal
16
INT0
I
Interrupt request signal input from the AV decoder
17
INT1
I
Interrupt request signal input from the ARP
18
INT2
I
Interrupt request signal input from the servo DSP
19
INT3
I
Interrupt request signal input terminal Not used
20
INT4
I
Interrupt request signal input from the system controller
21 to 23
INT5 to INT7
I
Interrupt request signal input terminal Not used
24
VCC
—
Power supply terminal (+3.3V)
25
SI0
I
Serial data input from the system controller
26
SO0
O
Serial data output to the system controller
27
SC0
O
Serial clock signal output to the system controller
28
SI1
I
Serial data input from the audio DSP
29
SO1
O
Serial data output to the audio DSP
30
SC1
O
Serial clock signal output to the audio DSP
31
SI2
I
Serial data input terminal (for test)
32
SO2
O
Serial data output terminal (for test)
33
DSENS
—
Not used
34
VSS
—
Ground terminal
35
XRST
O
System reset signal output “L”: reset
36
XARPRST
O
Reset signal output to the ARP “L”: reset
37
RGBSEL/MICMUTE
—
Not used
38
SDA
I/O
Two-way data bus with EEPROM
39
SCL
O
Serial clock signal output to the EEPROM
40
TRM+/XKRRST
—
Not used
41
EUROV/Y/CLAPSW1
—
Not used
42
DISCEXT/CLPSW0
—
Not used
43
MD0
I
Mode select 0 signal input terminal
44
MD1
I
Mode select 1 signal input terminal
45
MD2
I
Mode select 2 signal input terminal
46
DREQ0
I
Request 0 signal input from the AV decoder
47
DACK0
O
Acknowledge 0 signal output to the AV decoder
48
XDRVMUTE
O
Drive mute signal output to the motor/coil drive
49
DREQ1
I
Request 1 signal input from the AV decoder
50
DACK1
O
Acknowledge 1 signal output to the AV decoder
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