DOWNLOAD Sony HCD-GV6 / HCD-GV8 / LBT-GV6 / LBT-GV8 Service Manual ↓ Size: 9.39 MB | Pages: 91 in PDF or view online for FREE

Model
HCD-GV6 HCD-GV8 LBT-GV6 LBT-GV8
Pages
91
Size
9.39 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-gv6-hcd-gv8-lbt-gv6-lbt-gv8.pdf
Date

Sony HCD-GV6 / HCD-GV8 / LBT-GV6 / LBT-GV8 Service Manual ▷ View online

57
HCD-GV6/GV8
Pin No.
Pin Name
I/O
Description
42, 43
BUS
O
Not used (open)
44
SHIMUKE
I
Destination setting terminal    “L”: chinese, “H”: others (fixed at “H” in this set)
45
BUS
I
Vertical synchronized signal input from the MPEG video/audio decoder (IC505)    “L” active
46
BUS XWRL
O
Not used (open)
47
LO.BOOST
O
Low boost control signal output terminal    Not used (open)
48
AUDIO MUTE
O
Audio muting on/off control signal output terminal    “L”: muting on    Not used (open)
49
LOAD OUT
O
Loading motor drive signal output terminal    Not used (open)
50
LOAD IN
O
Loading motor drive signal output terminal    Not used (open)
51
INSW
I
Disc detection (load in) switch input terminal    Not used (fixed at “H”)
52
OUTSW
I
Disc detection (load out) switch input terminal    Not used (fixed at “H”)
53
MODEL1
I
Destination setting terminal (fixed at “L”)
54
MODEL2
I
Destination setting terminal (fixed at “L”)
55
TBLL
O
Table motor drive signal output terminal    Not used (open)
56
TBLR
O
Table motor drive signal output terminal    Not used (open)
57 to 59
ENC1 to ENC3
I
Disc tray address detection signal input terminal    Not used
60, 61
NCO
O
Not used (open)
62
VCC
Power supply terminal (+5V)
63
NCO
O
Not used (open)
64
VSS
Ground terminal
65
VMUTE
O
Video muting on/off control signal output    “L”: muting on
66 to 71
A6 to A1
O
Address signal output for the external device    Not used (open)
72
UTOI
O
Not used (open)
73
TEST LED
O
LED drive signal output for the self diagnosis indicator (D502)    Normally: “L” (LED on)
74
TEST1
I
Setting terminal for the test mode 1 (for VCD check)
Normally: fixed at “H” (“L”: test mode)
75
TEST2
I
Setting terminal for the test mode 2 (for SERVO check)
Normally: fixed at “H” (“L”: test mode)
76
TEST3
I
Setting terminal for the test mode 3    Normally: fixed at “H” (“L”: test mode)
Not used (fixed at “H”)
77
DEVICE RESET
O
System reset signal output to the CXD3008Q (IC101), BA5974FP (IC102) and D/A converter 
(IC509)    “L”: reset
78
STANDBY
O
Standby on/off control signal output terminal    Not used (open)
79
FL CS
O
Chip select signal output terminal    Not used (open)
80
FLBLK
O
Blank control signal output terminal    Not used (open)
81 to 88
D7 to D0
I/O
Two-way data bus with the external device    Not used (open)
89
MIC CTRL
O
Mic control signal output terminal    Not used (fixed at “H”)
90 to 92
KEY1 to KEY3
I
Key input terminal    Not used (fixed at “H”)
93
NT/PAL
I
Video system select switch (S501) input terminal
“L”: PAL, “H”: NTSC, Center voltage: AUTO
94
MUSIC VOL
I
Volume input terminal    Not used (fixed at “H”)
95
KEY4
I
Key input terminal    Not used (fixed at “H”)
96
AVSS
Ground terminal (for A/D conversion)
97
MODE. SW
I
Mode switch input terminal    Not used (fixed at “H”)
98
VREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
99
AVCC
Power supply terminal (+5V) (for A/D conversion)
100
AMP. ON
O
Power amplifier on/off selection signal output terminal    Not used (open)
58
HCD-GV6/GV8
 VIDEO BOARD  IC505  CL680T-D1 (MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used (open)
2
VSS
Ground terminal
3
CD-BCK
I
CD decode bit clock signal (2.8224 MHz) input from the CXD3008Q (IC101)
4
CD-DATA
I
CD decode data input from the CXD3008Q (IC101)
5
CD-LRCK
I
CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC101)
6
CD-C2PO
I
CD decode C2 error data input from the CXD3008Q (IC101)
7 to 9
NC
O
Not used (open)
10 to 15
MD0 to MD5
I/O
Two-way data bus with the D-RAM (IC507)    Data input from the program ROM (IC506)
16
VSS
Ground terminal
17
MD6
I/O
Two-way data bus with the D-RAM (IC507)    Data input from the program ROM (IC506)
18
VDD3
Power supply terminal (+3.3V)
19
MD7
I/O
Two-way data bus with the D-RAM (IC507)    Data input from the program ROM (IC506)
20
VSS
Ground terminal
21
MD8
I/O
Two-way data bus with the D-RAM (IC507)    Data output to the program ROM (IC506)
22
VDD3
Power supply terminal (+3.3V)
23 to 28
MD9 to MD14
I/O
Two-way data bus with the D-RAM (IC507)    Data output to the program ROM (IC506)
29
MD15
I/O
Two-way data bus with the D-RAM (IC507)
30 to 36
NC
O
Not used (open)
37
MCE
O
Chip enable signal output to the program ROM (IC506)
38
MWE
O
Write enable signal output to the D-RAM (IC507)
39
VSS
Ground terminal
40
CAS
O
Column address strobe signal output to the D-RAM (IC507)
41
VDD3
Power supply terminal (+3.3V)
42
RAS0
O
Row address strobe signal output to the D-RAM (IC507)
43
RAS1
O
Row address strobe signal output terminal    Not used (open)
44, 45
MA10, MA9
O
Address signal output to the program ROM (IC506)
46
MA8
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
47
VSS
Ground terminal
48
MA7
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
49
VDD3
Power supply terminal (+3.3V)
50 to 52
MA6 to MA4
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
53
VSS
Ground terminal
54
MA3
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
55
VDD3
Power supply terminal (+3.3V)
56 to 58
MA2 to MA0
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
59
PGIO7
I/O
Not used (open)
60
RESET
I
Reset signal input from the CD mechanism controller (IC502)    “L”: reset
61
VDDMAX-IN
I
Fix the maximum input voltage each input terminal and in/out terminal
62 to 64
NC
O
Not used (open)
65
AGND-DAC
Ground terminal (for D/A converter)
66
AVDD-DAC
Power supply terminal (+3.3V) (for D/A converter)
67
COMPOS OUT
O
Composite video signal output terminal    Not used (open)
68
AGND-DAC
Ground terminal (for D/A converter)
69
Y-OUT
O
Luminance video signal output terminal
70
AVDD-DAC
Power supply terminal (+3.3V) (for D/A converter)
71
AGND-DAC
Ground terminal (for D/A converter)
59
HCD-GV6/GV8
Pin No.
Pin Name
I/O
Description
72
RREF
I
Fix the video signal output level control
73
VREF
O
Reference voltage (+1.235V) output terminal
74
AVDD-DAC
Power supply terminal (+3.3V) (for D/A converter)
75
C-OUT
O
Chrominance video signal output terminal
76
AGND-DAC
Ground terminal (for D/A converter)
77
CLK-SEL0
I
GCK (pin <z/b ) selection terminal    “L”: external clock, “H”: internal clock (fixed at “H”)
78
CLK-SEL1
I
DA-XCLK (pin ih) selection (1) terminal    Fixed at “H” in this set
79
CLK-SEL2
I
DA-XCLK (pin ih) selection (2) terminal    Fixed at “H” in this set
80
VSS
Ground terminal
81
RESERVED
I
Selection the operation clock 42.336 MHz (fixed at “L”)
82
VDD3
Power supply terminal (+3.3V)
83
DA-EMP
O
Not used (open)
84
RESERVED
O
Not used (open)
85
AGND-PLL
Ground terminal (for PLL system)
86
DA-XCLK
I
Main reference clock signal (16.9344 MHz=384fs) from the D/A converter (IC509)
87
AVDD-PLL
Power supply terminal (+3.3V) (for PLL system)
88
PGIO4
I/O
Not used (open)
89
PGIO5
I/O
Not used (open)
90
PGIO6
I/O
Not used (open)
91
PGIO0
I/O
Not used (open)
92
PGIO8
I/O
Not used (open)
93
PGIO2/VSYNC/
CSYNC
O
Vertical synchronized signal output to the CD mechanism controller (IC502)
94
AVDD-PLL
Power supply terminal (+3.3V) (for PLL system)
95 to 97
NC
O
Not used (open)
98
AGND-PLL
Ground terminal (for PLL system)
99
VSS
Ground terminal
100
NC
O
Not used (open)
101
PGIO3/HSYNC
I/O
Not used (open)
102
VDD3
Power supply terminal (+3.3V)
103
PGIO1/VCK-OUT
I/O
Not used (open)
104
VSS
Ground terminal
105
GCK
I
Not used (open)
106
VCK-IN
I
Main clock for video signal processor input from the D/A converter (IC509) (27 MHz)
107
GCKOUT/DA-EMP
O
Not used (open)
108
DA-LRCK
O
Digital audio L/R sampling clock signal (44.1 kHz) output to the D/A converter (IC509)
109
VDDMAX-OUT
O
Fix the maximum output voltage (+5V) certain output terminal
110
DA-DATA
O
Digital audio data output to the D/A converter (IC509)
111
DA-BCK
O
Digital audio bit clock signal (2.8224 MHz) output to the D/A converter (IC509)
112
HD-OUT
O
Serial data output to the CD mechanism controller (IC502)
113
HRDY
O
Ready signal output to the CD mechanism controller (IC502)
114
HINT
O
Interrupt request signal output to the CD mechanism controller (IC502)
115
CDG-SCK
I/O
Not used (open)
116
VSS
Ground terminal
117
HCK
I
Serial data transfer clock signal input from the CD mechanism controller (IC502)
118
VDD3
Power supply terminal (+3.3V)
119
HD-IN
I
Serial data input from the CD mechanism controller (IC502)
60
HCD-GV6/GV8
Pin No.
Pin Name
I/O
Description
120
VDD3
Power supply terminal (+3.3V)
121
HSEL
I
Command selection signal input from the CD mechanism controller (IC502)
122
CDG-SDATA
I
Not used (fixed at “L”)
123
CDG-VFSY
I
Not used (fixed at “L”)
124
CDG-S0S1
I
Not used (fixed at “L”)
125 to 128
NC
O
Not used (open)
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