Sony HCD-GTX88 / HCD-GTX88BP Service Manual ▷ View online
69
HCD-GTX88/GTX88BP
IC902 NJM2760V-TE2 (PANEL Board)
IC1100 NJM4565M (MIC Board)
A
B
1
A OUTPUT
2
A -INPUT
3
A +INPUT
4
V-
7 B OUTPUT
6 B -INPUT
5 B +INPUT
8 V+
BPF1IN2
DET
IN1
1
IN2
2
BPF2IN1 4
BPF2IN2 5
18
BPF3OUT
15
BPF1IN1
19
BPF2OUT
20
BPF
DET
BPF3IN1
6
BPF3IN2
7
BPF2OUT
14
BPF
DET
BPF4IN1 8
BPF4IN2
9
BPF1OUT
13
BPF
DET
GND 10
NC
12
BUF1OUT
3
VCC
11
RECOUT
17
BPF4OUT
16
BPF
DET
70
HCD-GTX88/GTX88BP
• IC PIN DESCRIPTIONS
IC101 TC94A70FG-008 (S, D) (RF AMP, FOCUS/TRACKING ERROR AMP, DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO
PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (BD91 BOARD)
PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (BD91 BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
AVSS3
—
Ground pin
2
RFZi
I
RF ripple zero crossing signal input
3
RFRP
O
RF ripple signal output
4
SBAD/RFDC
O
Sub beam addition signal or RF peak detection signal output
Not used in this set. (Open)
5
FEi
O
Focus error signal output Not used in this set. (Open)
6
TEi
O
Tracking error signal output
7
TEZi
I
Tracking error zero crossing signal input
8
AVDD3
—
Power supply pin (+3.3 V)
9
FOo
O
Focus coil drive signal output
10
TRo
O
Tracking coil drive signal output
11
VREF
I
Reference voltage (+1.65 V) input
12
FMO
O
Sled motor drive signal output
13
DMO
O
Spindle motor drive signal output
14
VSSP3
—
Ground pin
15
VCOi
I
VCO control voltage input
16
VDDP3
—
Power supply pin (+3.3 V)
17
VDD1
—
Power supply pin (+1.5 V)
18
VSS1
—
Ground pin
19
FGiN
I
FG signal input Not used. (Connected to ground.)
20
IO0 (/HSO)
I
Disc inner position detection signal input
21
IO1 (/UHSO)
O
Not used in this set. (Open)
22
XVSS3
—
Ground pin
23
XI
I
System clock input (16.9344 MHz)
24
XO
O
System clock output (16.9344 MHz)
25
XVDD3
—
Power supply pin (+3.3 V)
26
DVSS3
—
Ground pin
27
RO
O
Analog audio (R-ch) signal output
28
DVDD3
—
Power supply pin (+3.3 V)
29
DVR
O
Reference voltage (+1.65 V) output
30
LO
O
Analog audio (L-ch) signal output
31
DVSS3
—
Ground pin
32
VDDT3
—
Power supply pin (+3.3 V)
33
VSS1
—
Ground pin
34
VDD1
—
Power supply pin (+1.5 V)
35
VDDM1
—
Power supply pin (+1.5 V)
36
SRAMSTB
I
S-RAM standby mode control signal input Fixed at “L” in this set.
37
RST
I
Reset signal input from the system controller “L”: reset
38, 39
BUS0, BUS1
I/O
Serial data input/output from the system controller or USB controller
40
BUS2 (SO)
I/O
Serial data input/output from the system controller or USB controller
41
BUS3 (SI)
I/O
Serial data input/output from the system controller or USB controller
42
BUCK (CLK)
I
Serial data transfer clock signal input from the system controller or USB controller
43
CCE
I
Chip enable signal input from the system controller or USB controller
44
TEST
I
Setting pin for test mode Normally fixed at “L”
45
IRQ
I
Interrupt request signal input
46
AoUT3 (PO4)
O
Request signal output to the USB controller Not used in this set. (Open)
47
AoUT2 (PO5)
O
Audio data output to the USB controller
48
PIO0
O
Request signal output to the system controller or USB controller
49
PIO1
O
ST REQ signal output
50
PIO2
O
Not used in this set. (Open)
71
HCD-GTX88/GTX88BP
Pin No.
Pin Name
I/O
Pin Description
51
PIO3
I
Gate signal input from the USB controller
52
VSS1
—
Ground pin
53
VDDT3
—
Power supply pin (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used in this set. (Open)
56
IPF
O
Not used in this set. (Open)
57
SFSY/LOCK
O
Not used in this set. (Open)
58
ZDET
O
Zero detection signal output Not used in this set. (Open)
59
GPIN
I
Not used. (Connected to ground.)
60
MS
I
Microcomputer interface mode selection signal input Fixed at “H” in this set.
61
DOUT (PO6)
O
Digital audio data output Not used in this set. (Open)
62
AOUT1 (PO7)
O
Audio data output Not used in this set. (Open)
63
BCK (PO8)
O
Bit clock signal output to the USB controller
64
LRCK (PO9)
O
L/R sampling clock signal output
65
AIN (PI4)
I
Digital audio data input from the USB controller
66
BCKi (PI5)
I
Bit clock signal input from the USB controller
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller
68
VDD1
—
Power supply pin (+1.5 V)
69
VSS
—
Ground pin
70
AWRC
—
Not used in this set. (Open)
71
PVDD3
—
Power supply pin (+3.3 V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output
73
TMAXS
O
TMAX detection signal output Not used in this set. (Open)
74
TMAX
O
TMAX detection signal output
75
LPFN
I
Inverted signal input from the operation amplifier for PLL loop filter
76
LPFo
O
Signal output from the operation amplifier for PLL loop filter
77
PVREF
I
Reference voltage (+1.65 V) input
78
VCOF
O
VCO filter output
79
PVSS3
—
Ground pin
80
SLCo
O
EFM slice level output
81
RFi
I
RF signal input
82
RFRPi
I
RF ripple signal input
83
RFEQo
O
EFM slice level output
84
VRo
O
Reference voltage (+1.65 V) output
85
RESiN
O
External resistor connection pin
86
VMDiR
O
Reference voltage (+1.65 V) output for automatic power control circuit
87
TESTR
O
Low-pass filter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplification input
89
RFo
O
RF signal generation amplification output
90
RVDD3
—
Power supply pin (+3.3 V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
—
Ground pin
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
96
FPi2 (D)
I
Main beam (D) input from the optical pick-up block
97
FPi1 (B)
I
Main beam (B) input from the optical pick-up block
98
TPi (F)
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection pin
100
TNi (E)
I
Sub beam (E) input from the optical pick-up block
72
HCD-GTX88/GTX88BP
IC401 M30622MEP-A75FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4))
Pin No.
Pin Name
I/O
Pin Description
1
XRST
O
Reset signal output to the digital signal processor “L”:reset
2
MMUTE
O
Control port for the digital signal processor motor driver mute
3
CD CCE
O
Chip enable contor port to the digital signal processor
4
SIRCS
I
Remote control signal input
5
CD CLK
O
Serial date transfer clock signal output to the digital signal processor
6
MP3 IREQ
I
Digital signal decoder request pin to master control
7
SOURCE SEL1
O
Select function input for effector mode (CD/USB/Video in: “L”,
Tuner/Tape/Audio in: “H”)
8
BYTE
—
Ground pin
9
CNVss
—
Ground pin
10
XC IN
I
Sub system clock input (32.768 kHz)
11
XC OUT
O
Sub system clock output (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal IC “L”: reset After the power
supply rises, “L” is input for several hundreds msec and then change to “H”.
13
X OUT
O
Main system clock output (5 MHz)
14
VSS
—
Ground pin
15
X IN
I
Main system clock input (5 MHz)
16
VCC
—
Power supply pin (+3.3 V)
17
NMI
I
Non-maskable interrupt input
18
SOURCE SEL2
O
Select function input for effector mode (CD/USB/Tuner/Tape: “H”,
Audio in/Video in: “L”)
19
SBSY
I
Subcode sync detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal IC “L”: AC Cut detected
21
BUS3
I/O
Data bus line for CD communication with master control
22
BUS2
I/O
Data bus line for CD communication with master control
23
BUS1
I/O
Data bus line for CD communication with master control
24
BUS0
I/O
Data bus line for CD communication with master control
25
EFFECTOR S0
O
Effector circuitry delay time selection bit 0 signal output
26
EFFECTOR S1
O
Effector circuitry delay time selection bit 1 signal output
27
EFFECTOR S2
O
Effector circuitry delay time selection bit 3 signal output
28
EFFECTOR SEL
O
Effector circuity bypass control signal output “H”: bypass
29
IIC CLK
I/O
Clock signal for IIC communication between Master controller and Display controller
30
IIC DATA
I/O
Data signal for IIC communication between Master controller and Display controller
31
USBRST
O
Reset signal output to USB control IC “L”: reset
32
CD POWER
O
Power on/off control signal output to BU section “H”: power on
33
STBY LED/FAN
O
LED drive signal output of power indicator and fan on/off control port
CONTROL
34
USB SERIAL CTS0
I
Serial send control signal input from USB IC
35
USB SERIAL TXD0
O
UART serial transmission data line signal output to USB IC
36
USB SERIAL RXD0
I
UART serial reception data line signal output from USB IC
37
GC RESET
O
Reset signal output to display control IC “L”: reset
38
USB SERIAL RTS0
O
Serial receive control output from USB IC
39
SEL SW
O
USB and CD control switch CD (H)/USB (L)
40
USB PWR
O
Power on/off control signal output to USB section Power On: H
41
OPEN SW
I
Eject detection signal input from the CD mechanism
42
TBL SENSE
I
Disc tray position detection signal input from the CD mechanism
43
E-3
I
Disc tray status detection signal input from the CD mechanism
44
E-2
I
Disc tray status detection signal input from the CD mechanism
45
E-1
I
Disc tray status detection signal input from the CD mechanism
46
TMF
O
CD mechanism turning motor control signal output
47
TMR
O
CD mechanism turning motor control signal output
48
LMF
O
CD mechanism loading motor control signal output
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