Sony HCD-GTX66 / HCD-GTX77 / HCD-GTX77BP / MHC-GTX66 / MHC-GTX77 / MHC-GTX77BP Service Manual ▷ View online
69
HCD-GTX66/GTX77/GTX77BP
IC401 M30622MGP-A57FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4))
Pin No.
Pin Name
I/O
Pin Description
1
XRST
O
Reset signal output to the digital signal processor “L”:reset
2
MMUTE
O
Control port for the digital signal processor motor driver mute
3
CD CCE
O
Chip enable contor port to the digital signal processor
4
SIRCS
I
Remote control signal input
5
CD CLK
O
Serial date transfer clock signal output to the digital signal processor
6
MP3 IREQ
I
Digital signal decoder request pin to master control
7
SOURCE SEL1
O
Select function input for effector mode (CD/USB/Video in: “L”,
Tuner/Tape/Audio in: “H”)
8
BYTE
—
Ground pin
9
CNVss
—
Ground pin
10
XC IN
I
Sub system clock input (32.768 kHz)
11
XC OUT
O
Sub system clock output (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal IC “L”: reset After the power
supply rises, “L” is input for several hundreds msec and then change to “H”.
13
X OUT
O
Main system clock output (5 MHz)
14
VSS
—
Ground pin
15
X IN
I
Main system clock input (5 MHz)
16
VCC
—
Power supply pin (+3.3 V)
17
NMI
I
Non-maskable interrupt input
18
SOURCE SEL2
O
Select function input for effector mode (CD/USB/Tuner/Tape: “H”,
Audio in/Video in: “L”)
19
SBSY
I
Subcode sync detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal IC “L”: AC Cut detected
21
BUS3
I/O
Data bus line for CD communication with master control
22
BUS2
I/O
Data bus line for CD communication with master control
23
BUS1
I/O
Data bus line for CD communication with master control
24
BUS0
I/O
Data bus line for CD communication with master control
25
EFFECTOR S0
O
Effector circuitry delay time selection bit 0 signal output
26
EFFECTOR S1
O
Effector circuitry delay time selection bit 1 signal output
27
EFFECTOR S2
O
Effector circuitry delay time selection bit 3 signal output
28
EFFECTOR SEL
O
Effector circuity bypass control signal output “H”: bypass
29
IIC CLK
I/O
Clock signal for IIC communication between Master controller and Display controller
30
IIC DATA
I/O
Data signal for IIC communication between Master controller and Display controller
31
USBRST
O
Reset signal output to USB control IC “L”: reset
32
CD POWER
O
Power on/off control signal output to BU section “H”: power on
33
STBY LED/FAN
O
LED drive signal output of power indicator and fan on/off control port
CONTROL
34
USB SERIAL CTS0
I
Serial send control signal input from USB IC
35
USB SERIAL TXD0
O
UART serial transmission data line signal output to USB IC
36
USB SERIAL RXD0
I
UART serial reception data line signal output from USB IC
37
GC RESET
O
Reset signal output to display control IC “L”: reset
38
USB SERIAL RTS0
O
Serial receive control output from USB IC
39
SEL SW
O
USB and CD control switch CD (H)/USB (L)
40
USB PWR
O
Power on/off control signal output to USB section Power On: H
41
OPEN SW
I
Eject detection signal input from the CD mechanism
42
TBL SENSE
I
Disc tray position detection signal input from the CD mechanism
43
E-3
I
Disc tray status detection signal input from the CD mechanism
44
E-2
I
Disc tray status detection signal input from the CD mechanism
45
E-1
I
Disc tray status detection signal input from the CD mechanism
46
TMF
O
CD mechanism turning motor control signal output
47
TMR
O
CD mechanism turning motor control signal output
48
LMF
O
CD mechanism loading motor control signal output
70
HCD-GTX66/GTX77/GTX77BP
Pin No.
Pin Name
I/O
Pin Description
49
LMR
O
CD mechanism loading motor control signal output
50
STBY RELAY
O
Main power on/off control signal output “H”: power on
51
ATRIG
O
Deck A side trigger plunger drive signal output “H”: plunger on
52
A HALF
I
Deck A cassette detection signal input “H”: cassette detected
53
CAPM+
O
Capstan motor drive signal output
54
B TRIG
O
Deck B side trigger plunger drive signal output “H”: plunger on
55
REC BIAS
O
Recording bias on/off control signal output “H”: bias on
56
TC RELAY
O
Recording/playback selection signal output “H”: recording, “L”: playback
57
PB A/B
O
Deck A/B playback selection signal output “H”: Deck A, “L”: Deck B
58
ALC
O
Automatic limiter control signal output “H”: limiter ON
59
REC MUTE
O
Recording muting on/off control signal output “L”: muting on
60
TC MUTE
O
Tape playback muting on/off control signal output “H”: muting on
61
UNDER VOLTAGE DET
I
Under-voltage protection detection signal input “H”: under-voltage detected
62
VCC
—
Power supply pin (+3.3 V)
63
OVER VOLTAGE DET
I
Over-voltage protection detection signal input “L”: over-voltage detected
64
VSS
—
Ground pin
65
CD USB MUTE
O
CD and USB analog muting on/off control signal output “L”: muting on
66
LINE MUTE
O
Line muting on/off control signal output “L”: muting on
67
STK MUTE
O
Power amplifier and sub woofer amplifier on/off control signal output
“H”: amplifier on
68
HP MUTE
O
Headphone muting on/off control signal output “L”: muting on
69
PROTECTOR
I
Speaker protect detection signal input from speaker protect circuit “L”: protector on
70
FRONT RELAY
O
Relay drive signal output for the front speakers “H”: relay on
71
LINK RELAY
O
Surround speaker mode control signal output “H”: link, ”L”: matrix surround 1/2
Not used in this set.
72
SW SPK RELAY
O
Relay drive signal output for the passive sub woofer output “H”: relay on
Not used in this set.
73
DISPLAY KEY
I
DISPLAY key press detection signal input (Interrupt input)
74
POWER KEY
I
POWER key press detection signal input (Interrupt input)
75
Z GROOVE FREQ
O
Selector port to turn the Z-groove frequency response circuity
76
NO USE
I
Not used in this set. (Connected to ground.)
77
CTRL 3
O
Effector circuity mode control 3 signal output “H”: Chorus/Effector Off,
“L”: Flanger/Delay.
78
CTRL 1
O
Effector circuity mode control 1 signal output “H”: Delay/Effector Off,
“H”: Flanger/Chorus.
79
M61530 DATA
O
Serial data signal output to 4-ch volume IC Not used in this set.
80
M61530 CLK
O
Serial data transfer clock signal output to 4-ch volume IC Not used in this set.
81
M61529 DATA
O
Serial data signal output to audio signal processor
82
M61529 CLK
O
Serial data transfer clock signal output to audio signal processor
83
NO USE
I
Not used in this set. (Connected to ground.)
84
ST CE
O
PLL chip enable signal output to the tuner unit
85
ST DIN/MC DOUT
I
PLL serial data signal input from the tuner unit
86
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
87
ST DOUT/MC DIN
O
PLL serial data signal output to the tuner unit
88
FAN HI SPEED
O
Fan high speed control signal output for Themal VACS “L”: Fan high speed on.
89
A SHUT
I
Shut off detection signal input from deck A side reel pulse detector (A/D input)
90
B SHUT
I
Shut off detection signal input from deck A side reel pulse detector (A/D input)
91
B HALF
I
Deck B cassette detection, forward side recording tab detection and reverse side
recording tab detection signal input (A/D input)
92
MODEL IN
I
Model setting pin (A/D input)
93
DEST IN
I
Destination setting pin (A/D input)
94
THERMA VACS
I
Temperature detection signal input from thermistor (A/D input)
71
HCD-GTX66/GTX77/GTX77BP
Pin No.
Pin Name
I/O
Pin Description
95
SW VOL IN
I
Subwoofer volume level detection signal input from subwoofer volume jog
(A/D input) Not used in this set.
96
AVSS
I
Ground pin (for A/D conversion)
97
SW ON LED
O
LED drive signal output of SUB WOOFER ON indicator on sub woofer
“H”: LED ON Not used in this set.
98
VREF
I
A/D Converter reference voltage input (+3.3 V)
99
AVCC
—
Power supply pin (+3.3 V) (for A/D conversion)
100
HP DET
I
Headphone connection detection signal input “H”: headphone connected
72
HCD-GTX66/GTX77/GTX77BP
IC901 TMP92CD28AFG-2CB4 (USB CONTROLLER) (USB BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
RESET
I
Reset signal input from the system controller “L”: reset
2
PC0/INT0
I
Ready to send signal input from the system controller
3
PC1/INT1
O
Not used in this set. Connected to ground.
4
PC2/INT2/TB1IN0
O
Not used in this set. Connected to ground.
5
PC3/INT3
I
Function selection signal input Fixed at “L” in this set.
6
DVCC3B
—
Power supply pin (+3.3 V)
7
PC6/XT1
O
Not used in this set. (Open)
8
PC7/XT2
O
Not used in this set. (Open)
9
PWE
O
Not used in this set. (Open)
10
DVSS1B
—
Ground pin
11
DVCC1B
—
Power supply pin (+3.3 V)
12
RVOUT1
O
Reference voltage (+3.3 V) output pin
13, 14
RVIN
I
Reference voltage (+3.3 V) input pin
15
RVOUT2
O
Reference voltage (+3.3 V) output pin
16
DVCC1A
—
Power supply pin (+3.3 V)
17
DVSS1A
—
Ground pin
18 to 25
P00/D0 to P07/D7
I/O
Two-way data bus with the S-RAM
26
DVSS
—
Ground pin
27
DVCC3A
—
Power supply pin (+3.3 V)
28 to 35
P10/D8 to P17/D15
I/O
Two-way data bus with the S-RAM
36
P40/A0
O
Address signal output pin Not used in this set. (Open)
37 to 43
P41/A1 to P47/A7
O
Address signal output to the S-RAM
44
DVSS
—
Ground pin
45
DVCC3A
—
Power supply pin (+3.3 V)
46 to 54
P50/A8 to P60/A16
O
Address signal output to the S-RAM
55 to 58
P61/A17 to P64/A20
O
Serial data output to the CD-MP3 processor
59
P65/A21
O
Serial data transfer clock signal output to the CD-MP3 processor
60
P66/A22
O
Chip enable signal output to the CD-MP3 processor
61
P67/A23
O
Not used in this set. (Open)
62
DVSS
—
Ground pin
63
DVCC3A
—
Power supply pin (+3.3 V)
64
P70/RD
O
Output enable signal output to the S-RAM
65
P71/SRWR
O
Write enable signal output to the S-RAM
66
P72/SRLLB
O
Lower-byte control signal output to the S-RAM
67
P73/SRLUB
O
Upper-byte control signal output to the S-RAM
68
P74/TA0IN
O
Not used in this set. (Open)
69
P80/CS0/TA1OUT (BOOT)
I
Boot mode selection signal input “L”: boot mode
70
P82/CS2
I
Chip select signal output to the S-RAM
71
P83/CS3/WAIT/TA5OUT
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input Fixed at “H” in this set.
73
X2
O
System clock output (9 MHz)
74
DVSS
—
Ground pin
75
X1
I
System clock input (9 MHz)
76
DVCC3A
—
Power supply pin (+3.3 V)
77
P75/USBOC
I
Over current detection signal input
78
P76/USBPON
O
USB VBUS power on/off control signal output “H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D–
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input Fixed at “H” in this set.
82
P77/X1USB
O
Not used in this set. (Open)
83
DVSS
—
Ground pin
84
PF0/TXD0
O
Clear to send signal output to the system controller
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