Sony HCD-GTX66 / HCD-GTX77 / HCD-GTX77BP / MHC-GTX66 / MHC-GTX77 / MHC-GTX77BP Service Manual ▷ View online
65
HCD-GTX66/GTX77/GTX77BP
IC1503 TC74LVX4051FT (EFFECTOR Board)
IC915 R5523N001B-TR-F (USB Board)
IC1501 M65850FP-E1 (EFFECTOR Board)
1
EN
2
GND
3
FLG
4
IN
5
OUT
GATE
CONTROL
UVLO
THERMAL
SHUTDOWN
CURRENT
LIMIT
FLAG
DELAY
OSCILLATOR
1/2 VCC
AUTO
RESET
LPF1
MAIN
CONTROL
A/D
20KBIT
SRAM
LPF2
D/A
2
3
4
5
6
7
8
9
10
11
15
14
13
12
CLOCK
RESET
MO
MI
D1
D0
DO1
VCC
16
NC
CLOCK
REF
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1IN
1
NC
LPF1OUT
OP1OUT
OP1IN
CC1
CC2
GND
1
D4
2
D6
3
COM
4
D7
5
D5
6
INH
7
VEE
8
GND
9
C
10
B
11
A
12
D3
13
D0
14
D1
15
D2
16
VCC
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
OUT
C
IN
LOGIC LEVEL CONVERTER
66
HCD-GTX66/GTX77/GTX77BP
IC902 NJM2760V-TE2 (PANEL Board)
IC1100 NJM4558M (MIC Board)
A
B
1
A OUTPUT
2
A -INPUT
3
A +INPUT
4
V-
7 B OUTPUT
6 B -INPUT
5 B +INPUT
8 V+
BPF1IN2
DET
IN1
1
IN2
2
BPF2IN1 4
BPF2IN2 5
18
BPF3OUT
15
BPF1IN1
19
BPF2OUT
20
BPF
DET
BPF3IN1
6
BPF3IN2
7
BPF2OUT
14
BPF
DET
BPF4IN1 8
BPF4IN2
9
BPF1OUT
13
BPF
DET
GND 10
NC
12
BUF1OUT
3
VCC
11
RECOUT
17
BPF4OUT
16
BPF
DET
67
HCD-GTX66/GTX77/GTX77BP
• IC PIN DESCRIPTIONS
IC101 TC94A70FG-008 (S, D) (RF AMP, FOCUS/TRACKING ERROR AMP, DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO
PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (BD91 BOARD)
PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (BD91 BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
AVSS3
—
Ground pin
2
RFZi
I
RF ripple zero crossing signal input
3
RFRP
O
RF ripple signal output
4
SBAD/RFDC
O
Sub beam addition signal or RF peak detection signal output
Not used in this set. (Open)
5
FEi
O
Focus error signal output Not used in this set. (Open)
6
TEi
O
Tracking error signal output
7
TEZi
I
Tracking error zero crossing signal input
8
AVDD3
—
Power supply pin (+3.3 V)
9
FOo
O
Focus coil drive signal output
10
TRo
O
Tracking coil drive signal output
11
VREF
I
Reference voltage (+1.65 V) input
12
FMO
O
Sled motor drive signal output
13
DMO
O
Spindle motor drive signal output
14
VSSP3
—
Ground pin
15
VCOi
I
VCO control voltage input
16
VDDP3
—
Power supply pin (+3.3 V)
17
VDD1
—
Power supply pin (+1.5 V)
18
VSS1
—
Ground pin
19
FGiN
I
FG signal input Not used. (Connected to ground.)
20
IO0 (/HSO)
I
Disc inner position detection signal input
21
IO1 (/UHSO)
O
Not used in this set. (Open)
22
XVSS3
—
Ground pin
23
XI
I
System clock input (16.9344 MHz)
24
XO
O
System clock output (16.9344 MHz)
25
XVDD3
—
Power supply pin (+3.3 V)
26
DVSS3
—
Ground pin
27
RO
O
Analog audio (R-ch) signal output
28
DVDD3
—
Power supply pin (+3.3 V)
29
DVR
O
Reference voltage (+1.65 V) output
30
LO
O
Analog audio (L-ch) signal output
31
DVSS3
—
Ground pin
32
VDDT3
—
Power supply pin (+3.3 V)
33
VSS1
—
Ground pin
34
VDD1
—
Power supply pin (+1.5 V)
35
VDDM1
—
Power supply pin (+1.5 V)
36
SRAMSTB
I
S-RAM standby mode control signal input Fixed at “L” in this set.
37
RST
I
Reset signal input from the system controller “L”: reset
38, 39
BUS0, BUS1
I/O
Serial data input/output from the system controller or USB controller
40
BUS2 (SO)
I/O
Serial data input/output from the system controller or USB controller
41
BUS3 (SI)
I/O
Serial data input/output from the system controller or USB controller
42
BUCK (CLK)
I
Serial data transfer clock signal input from the system controller or USB controller
43
CCE
I
Chip enable signal input from the system controller or USB controller
44
TEST
I
Setting pin for test mode Normally fixed at “L”
45
IRQ
I
Interrupt request signal input
46
AoUT3 (PO4)
O
Request signal output to the USB controller Not used in this set. (Open)
47
AoUT2 (PO5)
O
Audio data output to the USB controller
48
PIO0
O
Request signal output to the system controller or USB controller
49
PIO1
O
ST REQ signal output
50
PIO2
O
Not used in this set. (Open)
68
HCD-GTX66/GTX77/GTX77BP
Pin No.
Pin Name
I/O
Pin Description
51
PIO3
I
Gate signal input from the USB controller
52
VSS1
—
Ground pin
53
VDDT3
—
Power supply pin (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used in this set. (Open)
56
IPF
O
Not used in this set. (Open)
57
SFSY/LOCK
O
Not used in this set. (Open)
58
ZDET
O
Zero detection signal output Not used in this set. (Open)
59
GPIN
I
Not used. (Connected to ground.)
60
MS
I
Microcomputer interface mode selection signal input Fixed at “H” in this set.
61
DOUT (PO6)
O
Digital audio data output Not used in this set. (Open)
62
AOUT1 (PO7)
O
Audio data output Not used in this set. (Open)
63
BCK (PO8)
O
Bit clock signal output to the USB controller
64
LRCK (PO9)
O
L/R sampling clock signal output
65
AIN (PI4)
I
Digital audio data input from the USB controller
66
BCKi (PI5)
I
Bit clock signal input from the USB controller
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller
68
VDD1
—
Power supply pin (+1.5 V)
69
VSS
—
Ground pin
70
AWRC
—
Not used in this set. (Open)
71
PVDD3
—
Power supply pin (+3.3 V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output
73
TMAXS
O
TMAX detection signal output Not used in this set. (Open)
74
TMAX
O
TMAX detection signal output
75
LPFN
I
Inverted signal input from the operation amplifier for PLL loop filter
76
LPFo
O
Signal output from the operation amplifier for PLL loop filter
77
PVREF
I
Reference voltage (+1.65 V) input
78
VCOF
O
VCO filter output
79
PVSS3
—
Ground pin
80
SLCo
O
EFM slice level output
81
RFi
I
RF signal input
82
RFRPi
I
RF ripple signal input
83
RFEQo
O
EFM slice level output
84
VRo
O
Reference voltage (+1.65 V) output
85
RESiN
O
External resistor connection pin
86
VMDiR
O
Reference voltage (+1.65 V) output for automatic power control circuit
87
TESTR
O
Low-pass filter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplification input
89
RFo
O
RF signal generation amplification output
90
RVDD3
—
Power supply pin (+3.3 V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
—
Ground pin
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
96
FPi2 (D)
I
Main beam (D) input from the optical pick-up block
97
FPi1 (B)
I
Main beam (B) input from the optical pick-up block
98
TPi (F)
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection pin
100
TNi (E)
I
Sub beam (E) input from the optical pick-up block
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