Sony HCD-GNX100 Service Manual ▷ View online
53
HCD-GNX100
– CD Board –
IC301 TC94A34FG-002
33
34
35
36
37
38
39
40
41
42
1
8
43
61
62
63
64
60
59
56
52
50
47
46
45
44
48
49
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
2
3
4
5
6
7
58
57
55
53
51
12
13
14
15
16
54
CS/RAS/ADO2
AD15/CAS/PD12
SDO3/OE
WE/SDO1
PIO7/B
US3/IO7
PIO6/FI3/B
US2/IO7
PIO5/FI2/B
US1/IO5
PIO4/FI1/B
US0/IO4
Bus
Switch
PO11/BUCK/AD14
PO10/CCE/AD13
PO9/AD12
PO08/AD11
Gener
al
In/Output P
or
t
Address Calc.
2sets
Y-
P
o
inter
register
C-P
ointer
register
X-P
ointer
register
VDDM
SRMSTB
VDDT
AD10
AD9
ERAM
2k w
ord
CRAM
4k w
ord
CR
OM
4k w
ord
YRAM
4k w
ord
XRAM
4k w
ord
SRAM/
DRAM I/F
SRAM I/F
1Mbit
SRAM
X-Bus
Y-
B
u
s
PO07/AD7
PO06/AD6
PO05/AD5
AD8
VC0
Timing
Generator
PRAM
Instr
uction
Decoder
Prog
ram
Control
MCU
. I/F
register
XO • X1 • X2
Y0 •
Y1 •
Y2
MX
MY
MZ
MA
C
A0
A1
AX
A
Y
ALU
A2
A3
DIT
round & limit
round & limit
Au
d
io I/F
LRCKIA
BCKIA
SDI0
LRCKO
BCKO
SDO0
VSS
VDDT
MIACK
MICK
MIDIO
MILP
MICS
STANBY
RESET
VDDP
AD4/PO04
AD3/PO03
AD2/PO02
AD1/PO01
AD0/PO00
VSS
VDD
CK
O/PO13/AD16
VDDX
XO
TEST
VCOI
VSSX
XI
MIMD
VSSP
PIO3/IO3
PIO2/IO2
PIO1/SDI3/IO1
PIO0/SDI2/IO0
VSS
CKI/CLOCK/IRQ/FIO
VDD
TXO
SFSY/LRCKIB
SBSY/BCKIB
SDI1/D
A
T
A
POM
Sub code
I/F
CDP Cont
I/F
54
HCD-GNX100
7-26. IC Pin Function Descriptions
• IC101 CXD3059AR (RF AMP) (CD BOARD)
Pin No.
Pin Name
I/O
Description
1
MIRR
I/O
Not used (Open)
2
DFCT
I/O
Not used (Open)
3
FOK
I/O
Not used (Open)
4
VSS
—
Ground
5
LOCK
I/O
Not used (Open)
6
MDP
O
Spindle motor servo control output
7
SSTP
I
Disk innermost detection signal input
8
IOVSS1
—
Ground
9
SFDR
O
Sled drive signal output
10
SRDR
O
Sled drive signal output
11
TFDR
O
Tracking drive signal output
12
TRDR
O
Tracking drive signal output
13
FFDR
O
Focus drive signal output
14
FRDR
O
Focus drive signal output
15
IOVDD1
—
Power supply (+3.3V)
16
AVDD0
—
Power supply (+3.3V)
17
AVSS0
—
Ground
18
NC
—
Not used (Open)
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input
22
TEO
O
Tracking error signal output
23
FEI
I
Focus error signal input
24
FEO
O
Focus error signal output
25
VC
I/O
Center voltage output from RF amplifier block
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input
30
NC
—
Not used (Open)
31
AVDD4
—
Power supply (+3.3V)
32
RFDCO
O
RFDC signal output (Not used)
33
PDSENS
I
Reference voltage pin
34
AC_SUM
O
RFAC summing amplifier output
35
EG_IN
I
Equalizer circuit input
36
LD
O
APC LD drive signal output
37
PD
I
APC PD signal input
38
NC
—
Not used (Open)
39
RFC
I
Equalizer cut-off frequency adjustment pin
40
AVSS4
—
Ground
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input or EFM signal input
43
AVDD3
—
Power supply (+3.3V)
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparator voltage input
46
ASYO
O
EFM full-swing output
47
VPCO
O
Not used (Open)
48
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
55
HCD-GNX100
Pin No.
Pin Name
I/O
Description
49
AVSS3
—
Ground
50
CLTV
I
Multiplier VCO1 control voltage input
51
FILO
O
Master PLL (slave = digital PLL) filter output
52
FILI
I
Master PLL filter input
53
PCO
O
Master PLL charge pump output
54
AVDD5
—
Power supply (+3.3V)
55
DDVROUT
O
DC/DC converter output (+2.5V)
56
DDVRSEN
I
DC/DC converter output voltage monitor input
57
AVSS5
—
Ground
58
DDCR
I
DC/DC converter reset input
59
NC
—
Not used (Open)
60
BCKI
I
D/A interface bit clock input
61
PCMDI
I
D/A interface serial data input
62
LRCKl
I
D/A interface LR clock input
63
LRCK
O
D/A interface LR clock output f = Fs
64
VSS
—
Ground
65
PCMD
O
D/A interface serial data output
66
BCK
O
D/A interface bit clock output
67
VDD
—
Power supply (+2.5V)
68
EMPH
O
High when the playback disc has emphasis, low it has not
69
EMPHI
I
High when de-emphasis is ON, low when input OFF
70
IOVDD2
—
Power supply (+3.3V)
71
DOUT
O
Digital Out output
72
TEST
I
Test pin (Connected ground)
73
TEST1
I
Test pin (Connected ground)
74
IOVSS2
—
Ground
75
NC
—
Not used (Open)
76
XVSS
—
Ground
77
XTAO
O
Crystal oscillation circuit output
78
XTAI
I
Crystal oscillation circuit input
79
XVDD
—
Power supply (+2.5V)
80
AVDD1
—
Power supply (+3.3V)
81
AOUT1
O
L-ch analog output
82
VREFL
O
L-ch reference voltage
83
AVSS1
—
Ground
84
AVSS2
—
Ground
85
VREFR
O
R-ch reference voltage
86
AOUT2
O
R-ch analog output
87
AVDD2
—
Power supply (+3.3V)
88
NC
—
Not used (Open)
89
IOVDD0
—
Power supply (+3.3V)
90
RMUT
O
Not used (Open)
91
LMUT
O
Not used (Open)
92
NC
—
Not used (Open)
93
XTSL
I
Crystal selection input (Pull down)
94
IOVSS0
—
Ground
95
XTACN
I
Oscillation circuit control (H:Self-oscillation, L:oscillation stop)
96
SQSO
O
Not used (Open)
97
SQCK
I
SQSO readout clock input (Connected to +VDD(+3.3v))
98
SBSO
O
Not used (Open)
56
HCD-GNX100
Pin No.
Pin Name
I/O
Description
99
EXCK
I
Not used (Open)
100
XRST
I
System reset input from M30622MEP
101
SYSM
I
Mute input (Connected to ground)
102
DATA
I
Serial data input from M30622MEP
103
VSS
—
ground
104
XLAT
I
Latch input from M30622MEP
105
CLOCK
I
Serial data transfer clock input from M30622MEP
106
VDD
—
Power supply (+2.5V)
107
SENS
O
SENS output to M30622MEP
108
SCLK
I
SENS serial data readout clock input (Connected to +VDD(+3.3v))
109
ATSK
I/O
Not used (Open)
110
WFCK
O
Not used (Open)
111
XUGF
O
Not used (Open)
112
XPCK
O
Not used (Open)
113
GFS
O
Not used (Open)
114
C2PO
O
Not used (Open)
115
SCOR
O
High output when the sub code sync, S0 or S1, is detected
116
VDD
—
Power supply (+2.5V)
117
C4M
O
Not used (Open)
118
WDCK
O
Not used (Open)
119
COUT
I/O
Not used (Open)
120
NC
—
Not used (Open)
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