Sony HCD-GN88D / MHC-GN88D Service Manual ▷ View online
69
HCD-GN88D
Pin Name
Pin No.
I/O
Discription
103
GND25
—
Ground terminal (SDRAM I/O signal)
104
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
105
VCLK
I/O
System clock (not used)
106
XCK_I/O_SEL
I/O
5.1ch/downmix switch signal output
107
VS
O
S1 signal output
108
I/P SW
O
Progressive/interlace switch signal output
109
CDSEL
O
CD-DA selection signal output
110
MREQ
O
Audio muting request signal output
111
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
112
GNDP
—
Ground terminal (I/O signal)
113
MDI
O
Serial data output to the D/A converter
114
MC
O
Serial data clock output to the D/A converter
115
ML
O
Latch enable signal output to the D/A converter
116
HIRQ2_
I
Busy signal input from the EEPROM
117
VDAC_4B
—
Video DAC bias bit 4 (connected to the ground)
118
VDAC_VDD4
—
Power supply terminal (+3.3V) (Video DAC 4)
119
VDAC_4
O
VDAC output 4
120
VDAC_3B
—
Video DAC bias bit 3 (connected to the ground)
121
VDAC_VDD3
—
Power supply terminal (+3.3V) (Video DAC 3)
122
VDAC_3
O
VDAC output 3
123
VDAC_2B
—
Video DAC bias bit 2 (connected to the ground)
124
VDAC_VDD2
—
Power supply terminal (+3.3V) (Video DAC 2)
125
VDAC_2
O
VDAC output 2
126
VDAC_1B
—
Video DAC bias bit 1 (connected to the ground)
127
VDAC_VDD1
—
Power supply terminal (+3.3V) (Video DAC 1)
128
VDAC_1
O
VDAC output 1
129
VDAC_0B
—
Video DAC bias bit 0 (connected to the ground)
130
VDAC_VDD0
—
Power supply terminal (+3.3V) (Video DAC 0)
131
VDAC_0
O
VDAC output 0
132
VDAC_DVSS
—
Ground terminal (Video DAC digital system)
133
VDAC_DVDD
—
Power supply terminal (+3.3V) (Video DAC digital system)
134
VDAC_REFVDD
—
Power supply terminal (Video DAC reference)
135
VDAC_REF
I
Reference voltage input terminal(for Video DAC)
136
VDAC_REFVSS
—
Ground terminal (Video DAC reference)
137
XVSS
—
Ground terminal (crystal oscillator)
138
XOUT
O
Crystal oscillation signal output
139
XIN
I
Crystal oscillation signal input
140
XVDD
—
Power supply terminal (crystal oscillator)
141
AVSS2
—
Ground terminal (analog PLL)
142
AVDD2
—
Power supply terminal (+3.3V) (analog PLL)
143
AVDD1
—
Power supply terminal (+3.3V) (analog PLL)
144
AVSS1
—
Ground terminal (analog PLL)
145
VDD
—
Power supply terminal (+1.8V) (inside core)
146
GND
—
Ground terminal (inside core)
147
XCK
O
Audio system clock output
148
LRCK
O
LRCK signal output for audio
149
BCK
O
BCK signal output for audio
150
DATA0(DM)
O
Audio data(Down Mix signal) output
151
DATA1(FLR)
O
Audio data(Front L/R signal) output
152
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
153
GNDP
—
Ground terminal (I/O signal)
154
DATA2(SLR)
O
Audio data(Rear L/R signal) output
155
DATA3(CSW)
O
Audio data(Center/Subwoofer signal) output
156
IEC958
O
S/PDIF signal (not used)
157
DAI_DATA
I
Data input from ADC (not used)
70
HCD-GN88D
Description
Pin Name
Pin No.
I/O
158
DAI_BCK
I
BCK signal input from ADC (not used)
159
DAI_LRCK
I
LRCK signal input from ADC (not used)
160
I2C_CL
I/O
I2C clock bus
161
I2C_DA
I/O
I2C data bus
162
CS(ZIVA_E2P)
O
Chip select signal output to the EEPROM (IC204)
163
RXD1
I
Serial data input for check jig
164
TXD1
O
Serial data output for check jig
165
WRITE_CTRL(ZIVA_E2P)
O
Write control signal output to the EEPROM (IC204)
166
GNDP
—
Ground terminal (I/O signal)
167
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
168
SDDATA7
I
SDBus data7 input
169
SDDATA6
I
SDBus data6 input
170
SDDATA5
I
SDBus data5 input
171
SDDATA4
I
SDBus data4 input
172
GND
—
Ground terminal (inside core)
173
VDD
—
Power supply terminal (+1.8V) (inside core)
174
SDDATA3
I
SDBus data3 input
175
SDDATA2
I
SDBus data2 input
176
SDDATA1
I
SDBus data1 input
177
SDDATA0
I
SDBus data0 input
178
SDREQ
O
SDBus data request signal output
179
SDEN
I
SDBus data enable signal input
180
GNDP
—
Ground terminal (I/O signal)
181
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
182
SDERROR
I
SDBus data error signal input
183
SDCLK
I
SDBus data clock input
184
HIRQ1
I
Interrupt signal input from the mechanism controller (IC901)
185
DRVCLK
I
Serial data clock input from the mechanism controller (IC901)
186
DRVTX
I
Serial data input from the mechanism controller (IC901) and the EEPROM (IC204)
187
DRVRX
I
Serial data output to the mechanism controller (IC901) and the EEPROM (IC204)
188
DRVRDY
O
Ready signal input from the mechanism controller (IC901)
189
VNW
—
Power supply for 5V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux
191
RST_SPC
O
Reset signal output to the mechanism controller (IC901)
192
INT/EXT
O
Input selection signal output for SDBus or ADC (not used)
193
HCS2
O
Chip select signal output for Medusa (not used)
194
HCS1
I/O
Not used
195
HCS0
O
Chip select signal output to the external ROM (IC206)
196
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
197
TRST
I
Reset signal input
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset input
203
BUS CLK
I/O
Not used
204
GND
—
Ground terminal (inside core)
205
VDD
—
Power supply terminal (+1.8V) (inside core)
206
HA3
I/O
Address bus 3
207
HA2
I/O
Address bus 2
208
GNDP
—
Ground terminal (I/O signal)
71
HCD-GN88D
• IC701 TMC57929PGF-RDP (DVD DECODER) (DBM03 Board)
Pin No.
1, 2
3
4
5
6
7
8
9 to 14
15
16
17
18
19
20, 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
I/O
—
I/O
I
—
I
—
I
—
O
I
I
I
O
—
I
O
—
O
O
—
O
O
O
O
—
O
O
—
O
—
O
O
O
—
O
O
O
O
—
O
O
—
O
—
I
O
O
I
Pin Name
D5, D6
VSS
D7
A0
VDD
A1
VDD5V
A2 to A7
VSS
XWAIT
XRD
XWR
XCS
XINT0, XINT1
VDD
XHRS
HDB7
VSS
HDB8
HDB6
VDDS
HDB9
HDB5
HDBA
HDB4
VSS
HDBB
HDB3
VDD
HDBC
VDDS
HDB2
HDBD
HDB1
VSS
HDBE
HDB0
HDBF
XSAK
VDDS
XDCK
XSHD
VDD
REDY
VSS
XHAC
HINT
XS16
HA1
Description
Two-way data bus with CXP973064-226R
Ground
Two-way data bus with CXP973064-226R
Address signal input from CXP973064-226R
Power supply (+3.3V)
Address signal input from CXP973064-226R
Power supply (+5V)
Address signal input from CXP973064-226R
Ground
Not used
Read strobe signal input from CXP973064-226R
Write strobe signal input from CXP973064-226R
Chip select signal input from CXP973064-226R
Interrupt signal output to CXP973064-226R
Power supply (+3.3V)
Not used
Stream data signal output to ZIVA5X-C1F
Ground
Error flag signal output to ZIVA5X-C1F
Stream data signal output to ZIVA5X-C1F
Power supply (+5V)
Not used
Stream data signal output to ZIVA5X-C1F
Not used
Stream data signal output to ZIVA5X-C1F
Ground
Not used
Stream data signal output to ZIVA5X-C1F
Power supply (+3.3V)
Not used
Power supply (+5V)
Stream data signal output to ZIVA5X-C1F
Not used
Stream data signal output to ZIVA5X-C1F
Ground
Not used
Stream data signal output to ZIVA5X-C1F
Not used
Serial data effect flag signal output to ZIVA5X-C1F
Power supply terminal (+5V) (digital system)
Serial data transfer clock signal output to ZIVA5X-C1F
Header flag signal (Not used)
Power supply (+3.3V)
Not used
Ground
DVD mode: Serial data request signal input from ZIVA5X-C1F
Not used (Pull up)
Not used (Pull up)
Not used (Pull up)
72
HCD-GN88D
Pin No.
57
58
59, 60
61
62, 63
64
65
66 to 69
70
71
72
73 to 75
76
77
78
79, 80
81
82 to 87
88
89
90
91
92
93
94
95
96, 97
98
99
100
101, 102
103
104 to 106
107
108
109
110
111
112
113, 114
115
116
117
118, 119
120
121
122, 123
124
125
126, 127
I/O
I/O
—
I
—
I
—
I/O
I/O
—
I/O
—
I/O
O
—
O
O
—
O
—
O
—
O
O
O
O
O
I/O
—
I/O
—
I/O
—
I/O
O
—
O
—
O
—
—
I
I
I
—
—
I
—
O
I
I
Pin Name
XPDI
VDDS
HA0, HA2
VSS
HCS0, HCS1
VDD
DASP
MDB0 to MDB3
VSS
MDB4
VDD5V
MDB5 to MDB7
XMWR
VDD
XRAS
MA0, MA1
VSS
MA2 to MA7
VDD
MA8
VSS
MA9/MNT0
MNT1/MNT1
MNT2/MNT2
XMOE
XCAS
MDB8, MDB9
VSS
MDBA
VDD
MDBB, MDBC
VDD5V
MDBD to MDBF
GFS
VSS
APEO
VDD
DASYO
GNDA5
ASF1, AFS2
DASYI
RFDCC
RFIN
VCCA5, VCCA4
VCOR1
VCOIN
GNDA4, GNDA3
LPF5
VC1
LPF2, LPF1
Description
Not used (Pull up)
Power supply (+5V)
Not used (Pull up)
Ground (open)
Not used
Power supply (+3.3V)
Not used
Two-way data bus with the D-RAM
Ground
Two-way data bus with the D-RAM
Power supply (+5V)
Two-way data bus with the D-RAM
Write enable signal output to the D-RAM
Power supply (+3.3V)
Row address strobe signal output to the D-RAM
Address signal output to the D-RAM
Ground
Address signal output to the D-RAM
Power supply (+3.3V)
Address signal output to the D-RAM
Ground
Address signal output to the D-RAM
EEPROM ready signal output to CXP973064
Address signal output to the D-RAM
Output enable signal output to the D-RAM
Column address strobe signal output to the D-RAM
Two-way data bus with the D-RAM
Ground
Two-way data bus with the D-RAM
Power supply (+3.3V)
Two-way data bus with the D-RAM
Power supply (+5V)
Two-way data bus with the D-RAM
Guard frame sync signal output to CXP973064-226R
Ground
Absolute phase error signal output
Power supply (+3.3V)
RF binary signal output
Ground
Filter connected terminal for selection the constant asymmetry compensation
Analog signal input after integrated from the RF binary signal
Input terminal for adjusting DC cut high-pass filter for RF signal
RF signal input from the DVD/CD RF amplifier
Power supply (+3.3V)
VCO oscillating range setting resistor connected
VCO input
Ground
Signal output from the operation amplifier from PLL loop filter
Middle point voltage (+1.65V) input
Inverted signal input to the operation amplifier from PLL loop filter
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