Sony HCD-FL7D Service Manual ▷ View online
117
HCD-FL7D
Pin No.
Pin Name
I/O
Description
86
PB-A/B
O
Deck-A/B selection signal output “L”: deck-B, “H”: deck-A
87
EQ-H/N
O
Normal/high speed selection signal output “L”: normal speed, “H”: high speed
88
ALC
O
Automatic limiter control signal output “H”: limiter on
89
DIR-RST
O
Reset signal output to the digital audio interface receiver
90
S/W
O
SW phase control signal output terminal
91
A-SHUT
I
Shut off detection signal input from the deck-A side reel pulse detector
92
B-SHUT
I
Shut off detection signal input from the deck-B side reel pulse detector
93
B-HALF
I
Deck-B cassette detection signal input terminal “L”: cassette in, “H”: no cassette
94
MODEL-IN
I
Model setting terminal
95
SPEC-IN
I
Destination setting terminal
96
AVSS
—
Ground terminal
97
AMS-IN
I
Automatic music sensor detection signal input
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVCC
—
Power supply terminal (+3.3V)
100
AC-CUT
I
AC cut on/off detection signal input from the reset signal generator
“L”: AC cut on, “H”: AC cut off or checked
“L”: AC cut on, “H”: AC cut off or checked
118
HCD-FL7D
•
DSP BOARD IC601 CXD9720Q (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the digital audio interface receiver “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
5
VDDI
—
Power supply terminal (+3.3V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13 MHz)
10
VDDI
—
Power supply terminal (+3.3V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13 MHz)
13
MS
I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
18
SDI1
I
Audio serial data input from the digital audio interface receiver or digital audio processor
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
GP12
O
Clock signal output terminal Not used
38
GP13
O
Clock enable signal output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+3.3V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
119
HCD-FL7D
Pin No.
Pin Name
I/O
Description
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot trap signal input from the digital audio interface receiver
57
MOD1
I
PLL input frequency select terminal “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+3.3V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
Not used
Not used
68
DECODE
O
Decode signal output to the system controller
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+3.3V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used
88
XTRST
I
Simple emulation asychronous break input terminal Not used
89
TCK
I
Simple emulation clock signal input terminal Not used
90
TDI
I
Simple emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+3.3V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
120
HCD-FL7D
Pin No.
Pin Name
I/O
Description
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL reset signal input from the digital audio interface receiver
114
SDI3
I
Audio serial data input from the digital audio processor
115
SDI4
I
Audio serial data input from the digital audio processor
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117
TST2
—
Ground terminal
118
GP11
—
Not used
119
TST3
—
Ground terminal
120
VDDI
—
Power supply terminal (+3.3V)
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