Sony HCD-FL7D Service Manual ▷ View online
113
HCD-FL7D
•
MB BOARD IC901 CXP973064-223R (MACHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
EEP SO
O
Not used
2
SDEN
O
Serial data enable signal output to DVD/CD RF amplifier
3
DOCTRL/
ISBTEST
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
EEP WC
O
Not used
5
EEP SI
I/O
Two-way data bus with the EEPROM
6
EEP RDY
I
EEPROM ready signal input from the DVD decoder
7
FCS JMP 1
O
Focus jump 1 signal output to the motor/coil driver
8
FCS JMP 2
O
Focus jump 2 signal output to the motor/coil driver
9
SENS CD
I
Internal status (SENSE) signal input from the digital signal processor
10
LOAD +
O
Loading motor drive signal (loading in direction) output terminal Not used
11
LOAD –
O
Loading motor drive signal (loading out direction) output terminal Not used
12
XCS DVD
O
Chip select signal output to the DVD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the DVD decoder
22
INIT0 DVD
I
Interrupt signal input from the DVD decoder
23
INIT1 DVD
I
Interrupt signal input from the DVD decoder
24
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder
25
XRST DVD
O
Reset signal output to the DVD decoder “L”: reset
26
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27
LAT CD
O
Serial data latch pulse signal output to the digital signal processor
28
LD ON
O
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
29
MIRR
I
Mirror signal input from the digital signal processor
30
COUT CD
I
Numbers of track counted signal input from the digital signal processor
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS ZIVA
O
Chip select signal output to the DVD system processor
33
SI ZIVA
I
Serial data input from the DVD system processor
34
SO ZIVA
O
Serial data output to the DVD system processor
35
SCK ZIVA
O
Serial data transfer clock signal output to the DVD system processor
36
DRVIRQ
O
Interrupt request signal output to the DVD system processor
37
DRVRDY
O
Ready signal output to the DVD system processor
38
RST
I
System reset signal input from the DVD system processor “L”: reset
39
VSS
—
Ground terminal (digital system)
40
XTAL O
System clock output terminal (20 MHz)
41
EXTAL I
System clock input terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43, 44
SLED A, SLED B
O
Sled motor drive signal output
45
JIT OFFSET
O
Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
46
SDOUT DSD
O
Serial data output to the DSD decoder
47
SDIN DSD
I
Serial data input from the DSD decoder
48
READY DSD
I
Ready signal input from the DSD decoder “L”: ready
49
DATA CD
O
Serial data output to the digital signal processor
50
CLOK CD
O
Serial data transfer clock signal output to the digital signal processor
51
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder
52
SQSO
I
Subcode Q data input from the digital signal processor
114
HCD-FL7D
Pin No.
Pin Name
I/O
Description
53
MUTE DSD
O
Muting on/off control signal output to the DSD decoder “H”: muting on
54
SQCK
O
Subcode Q data reading clock signal output to the digital signal processor
55
VSS
—
Ground terminal (digital system)
56
TRAY IN
I
Disc tray in detection signal input terminal Not used
57
TRAY OUT
I
Disc tray out detection signal input terminal Not used
58
GFS DVD
I
Guard frame sync signal input from the DVD decoder
59
MUTE CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
60
MUTE 2D
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
61
SLED
I
Sled motor servo drive PWM signal input terminal
62
FG
I
Spindle motor control signal input
63
SP ON
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input from the DVD/CD RF amplifier
66
PI
I
Pull in signal input from the DVD/CD RF amplifier
67
FE
I
Focus error signal input from the DVD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
TSD
O
Thermal shut down signal output to the motor/coil driver
74
FOK CD
I
Focus OK signal input from the digital signal processor
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output “L”: DVD, “H”: SACD
78
I2C SIO
I/O
Communication data bus with the DVD system processor and system controller
79
I2C SCL
I/O
Communication data reading clock signal input or transfer clock signal output with the DVD
system processor and system controller
system processor and system controller
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
SDCLK RF
O
Serial data transfer clock signal output to the DVD/CD RF amplifier
83
SDATA RF
I/O
Two-way data bus with the DVD/CD RF amplifier
84
XWR
O
Write strobe signal output to the DVD decoder
85
XRD
O
Read strobe signal output to the DVD decoder
86
(PWE)
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89 to 96
A0 to A7
O
Address signal output to the DVD decoder
97
DSAVE
O
Motor/coil driver power save control signal output terminal Not used
98
XDRST
O
Reset signal output to the digital signal processor and DSD decoder “L”: reset
99
EEP WP
O
Write protect signal output to the EEPROM
100
EEP CLK
O
Clock signal output to the EEPROM
115
HCD-FL7D
•
MC BOARD IC101 M30622MGN-A07FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61520FP
2
AMP-CLK
O
Serial data transfer clock signal output to the M61520FP
3
AMP-LAT
O
Serial data latch pulse signal output to the M61520FP
4
SIRCS
I
Remote control signal input from the remote control receiver
5
DIG-TX
O
Serial data output to the audio digital signal processor and digital audio interface receiver
6
DSP-RX
I
Serial data input from the digital audio interface receiver
7
DIG-CLK
O
Serial data transfer clock signal output to the audio digital signal processor and
digital audio interface receiver
digital audio interface receiver
8
GND
—
Ground terminal
9
GND
—
Not used
10
XC-IN
I
Sub system clock input terminal (32.768 kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal input from the tuner unit
Used for AEP, UK models (Except AEP, UK models: Not used)
Used for AEP, UK models (Except AEP, UK models: Not used)
19
SCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used
20
DIR-INT
O
Interrupt request signal output to the digital audio interface receiver
21
CAPM-H/L
O
High/normal speed selection signal output of the capstan motor
“L”: high speed, “H”: normal speed
“L”: high speed, “H”: normal speed
22
CAPM-CNT1
O
Capstan motor drive signal output
23
A TRG
O
Deck-A side trigger plunger drive signal output “H”: plunger on
24
BU-PWM3
O
RFDC PWM signal output terminal Not used
25
B TRG
O
Deck-B side trigger plunger drive signal output “H”: plunger on
26
BU-PWM2
O
PWM signal output terminal Not used
27
A-HALF
I
Deck-A cassette detection signal input terminal “L”: no cassette, “H”: cassette in
28
BU-PWM1
O
Focus servo drive PWM signal output terminal Not used
29
IIC-CLK
I/O
IIC data reading clock signal input or transfer clock signal output with the fuluorescent indicator
driver and DVD system processor
driver and DVD system processor
30
IIC-DATA
I/O
IIC two-way data bus with the fuluorescent indicator driver
31
CAN'T USE
I
Not used
32
SQ-DATA-IN
I
Subcode Q data input terminal Not used
33
SQ-CLK
O
Subcode Q data reading clock signal output terminal Not used
34
SENS
I
Internal status detection monitor input terminal Not used
35
CD-DATA
O
Serial data output terminal Not used
36
CAN'T USE
I
Not used
37
CD-CLK
O
Serial data transfer clock signal output terminal Not used
38
POWER LED
O
LED drive signal output terminal
39
CLOCK-OUT
O
Clock (32.768 kHz) signal output terminal (for test mode) Not used
40
LDON(3STATE)
O
Laser diode on/off control signal output terminal Not used
116
HCD-FL7D
Pin No.
Pin Name
I/O
Description
41
M-RESET
I
Reset signal output to the fluorescent indicator tube driver and front panel controller
42
XLT
O
Serial data latch pulse output terminal Not used
43
XRST
O
Reset signal output to the DVD system processor “L”: reset
44, 45
VIDEO-MUTE,
VIDEO-MUTE2
O
Video muting on/off control signal output terminal “L”: muting on
46
NO-USE
—
Not used
47, 48
VOLUME A,
VOLUME B
I
Rotary encoder pulse input terminal
49
A PLAY
I
Deck-A play detection signal input terminal “H”: deck-A play
50
B PLAY
I
Deck-B play detection signal input terminal “H”: deck-B play
51
NO-USE
—
Not used
52
RDS-DATA
I
Serial data input from the tuner unit
Used for AEP, UK models (Except AEP, UK models: Not used)
Used for AEP, UK models (Except AEP, UK models: Not used)
53
ST MUTE
O
Tuner muting on/off control signal output to the FM/AM tuner unit
54
STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
55
TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
56
ST CE
O
PLL serial chip enable signal output to the tuner unit
57
ST DOUT
O
PLL serial data output to the tuner unit
58
ST DIN
I
PLL serial data input from the tuner unit
59
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
60
LINE MUTE
O
Line muting on/off control signal output “H”: muting on
61
DIR-CS
O
Chip enable signal output to the digital audio interface receiver
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT-TEST
O
Output terminal for the software test
64
VSS
—
Ground terminal
65
DIR-RX
I
Read data input from the digital audio interface receiver
66
DAC-LAT
O
Serial data latch pulse signal output to the D/A converter
67
DSP-ACK
I
Acknowledge signal input from the audio digital signal processor
68
DSP-CS
O
Chip select signal output to the audio digital signal processor
69
DSP-DECODE
I
Decode signal input from the audio digital signal processor
70
BTL 2.1CH D
O
BTL 2.1ch switching signal output terminal
71
BTL 2.1CH C
O
BTL 2.1ch switching signal output terminal
72
BTL 2.1CH B
O
BTL 2.1ch switching signal output terminal
73
DISPLAY KEY
I
Key input terminal (A/D input)
74
POWER KEY
I
Key input terminal (A/D input)
75
DIR-UNLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
76
BTL 2.1CH A
O
BTL 2.1ch switching signal output terminal
77
PROTECT
O
Speaker output over load detection signal input “L”: over load
78
FAN-CTRL
O
Fan motor drive signal output
79
CD-POWER
O
Power on/off control signal output for the CD/DVD section “H”: power on
80
STK-MUTE
O
Power amplifier on/off control signal output “L”: standby mode, “H”: power amplifier on
81
BIAS
O
Recording bias on/off control signal output “H”: bias on
82
TC-RELAY
O
Recording/playback selection signal output “L”: playback, “H”: recording
83
STBY-RELAY
O
Main power on/off control signal output “H”: power on
84
REC-MUTE
O
Recording muting on/off selection signal output terminal “L”: muting on
85
TC-MUTE
O
Playback muting on/off control signal output “H”: muting on
Click on the first or last page to see other HCD-FL7D service manuals if exist.