Sony HCD-DX80 Service Manual ▷ View online
46
HCD-DX80
IC602
BA3830F-E2
IC701
BA6956AN
2
3
14
1
f04
13 f05
12 f06
11 REC
LEVEL
10 VCC
15 f03
5
REC
NF
6
REC
IN
7
RESET
C
8
BIAS
C
9
GND1
4
16 f02
17 f01
18 RESET
R02
P01
LINE
NF
LINE
IN
REFFERENCE
CURRENT
BPF
DET
BPF
DET
BPF
DET
BPF
DET
DET
RESET
Bias
REFFERENCE
CURRENT
DET
DET
BPF
BPF
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
– PANEL Board –
– DRIVER Board –
47
HCD-DX80
•
MAIN BOARD IC501 M30620MCA-A95FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AUDIO OUT
ON/OFF
O
Audio output signal on/off control “H”: ON, “L”: OFF Not used (open)
2
STEREO
I
Stereo detection signal input from the LA1845 (IC11) “L”: Stereo in
3
TUNED
I
Tuning detection signal input from the LA1845 (IC11) “L”: Tuned in
4
SIRCS
I
Remote commander receiver signal input terminal
5
SUR1
O
Surround control signal output terminal not used (open)
6
SUR2
O
Surround control signal output terminal not used (open)
7
SUR3
O
Surround control signal output terminal not used (open)
8
GND
—
Ground terminal
9
GND
—
Ground terminal
10
XC IN
I
Sub system clock input terminal (32.768 kHz)
11
XC OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator (IC502) “L”: reset
13
X-OUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
X-IN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+5V)
17
NMI
I
For pull up terminal (connected to Ever +5V)
18
RDS-INT
I
RDS interrupt signal input terminal Not used (connected to ground)
19
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3017Q (IC101)
20
RDS-DATA
I
RDS data signal input terminal Not used (connected to ground)
21
ST-MUTE
O
Muting on/off control signal output to the LA1845 (IC11)
22
ST-CE
O
PLL chip enable signal output to the FM/AM PLL (IC51)
23
ST-DOUT
O
PLL serial data output to the FM/AM PLL (IC51)
24
BU-PWM3
O
RF data control signal output to the CXA2581N (IC103)
25
ST-DIN
I
PLL serial data input from the FM/AM PLL (IC51)
26
BU-PWM2
O
Tracking error control signal output to the CXA2581N (IC103)
27
ST-CLK
O
PLL serial data transfer clock signal output to the FM/AM PLL (IC51)
28
BU-PWM1
O
Focus error control signal output to the CXA2581N (IC103)
29
IIC-CLK
I/O
Shift clock signal input/output for the IIC bus
30
IIC-DATA
I/O
Data input/output terminal for the IIC bus
31
TXD1
O
Not used (open)
32
SQ-DATA
I
Subcode Q data input from the CXD3017Q (IC101)
33
SQ-CLK
O
Subcode Q data reading clock signal output to the CXD3017Q (IC101)
34
SENS
I
Internal status detection monitor input from the CXD3017Q (IC101)
35
CD-DATA
O
Serial data output to the CXD3017Q (IC101)
36
NC
—
Not used (fixed at “L”)
37
CD-CLK
O
Serial clock signal output to the CXD3017Q (IC101)
38
CD-POWER
O
CD power on/off control signal output “L”: on, “H”: off
39
CLOCK-OUT
O
Clock signal output terminal Not used (open)
40
HOLD
O
Automatic power control hold signal output to the CXA2581N (IC103)
41
M-RESET
O
Micom reset signal output to the liquid crystal display driver (IC601) “L”: reset
42
XLT
O
Serial data latch pulse output to the CXD3017Q (IC101)
43
XRST
O
CD reset signal output to the CXD3017Q (IC101) and BA5974FM (IC102) “L”: reset
44
LOAD-IN
O
Turn motor control signal output to the BA6956AN (IC701)
6-23. IC PIN FUNCTION DESCRIPTION
48
HCD-DX80
Pin No.
Pin Name
I/O
Description
45
LOAD-OUT
O
Turn motor control signal output to the BA6956AN (IC701)
46
OPEN-SW
I
Tray open detect signal input terminal “L”: open
47
CLOSE-SW
I
Tray close detect signal input terminal “L”: close
48
BU UP/DOWN-
SW
O
Pick-up up/down detect signal input terminal
49
T-SENS
I
CD table detect signal input from the RPI-321 (IC711)
50
NC
—
Not used (fixed at “L”)
51
A-TRIG
O
Deck-A trigger plunger on/off control signal output “H”: plunger on
52
B-TRIG
O
Deck-B trigger plunger on/off control signal output “H”: plunger on
53
AMS-IN
I
AMS signal input terminal “L”: AMS in
54
CAPM-H/L
O
High/normal speed selection signal output of the capstan motor
“H”: normal speed, “H”: high speed
“H”: normal speed, “H”: high speed
55
CAPM-CONTROL
O
Capstan motor on/off control signal output terminal “H”: motor on
56
A-PLAY
I
Detection input from the Deck-A play detect switch “H”: deck-A play
57
B-PLAY
I
Detection input from the Deck-B play detect switch “H”: deck-B play
58
TC-MUTE
O
Tape deck line muting on/off control output to the HA12226F (IC301) “H”: muting on
59
REC/PB/PAS
I
Recording/playback/pass selection signal input from the HA12226F (IC301)
“L”: recording mode, “Z”: playback mode, “H”: pass mode
“L”: recording mode, “Z”: playback mode, “H”: pass mode
60
NR-ON/OFF
O
Dolby NR on/off selection signal output to the HA12226F (IC301)
“H”: dolby on, “L”: dolby off
“H”: dolby on, “L”: dolby off
61
REC-MUTE
O
Recording muting on/off control signal output to the HA12226F (IC301) “H”: muting on
62
VCC
—
Power supply terminal (+5V)
63
SOFT TEST
O
Soft check terminal Not used (open)
64
VSS
—
Ground terminal
65
BIAS
O
Recording bias on/off control signal output to the HA12226F (IC301)
“H”: bias on, “L”: bias off
“H”: bias on, “L”: bias off
66
EQ-H/N
O
EQ high/normal selection signal output to the HA12226F (IC301)
“H”: high, “L”: normal
“H”: high, “L”: normal
67
PB-A/B
O
Deck-A/B selection signal output to the HA12226F (IC301)
“L”: deck-A, “H”: deck-B
“L”: deck-A, “H”: deck-B
68
ALC
O
ALC on/off control signal output to the HA12226F (IC301)
“L”: ALC on, “H”: ALC off
“L”: ALC on, “H”: ALC off
69
TC-RELAY
O
Tape deck relay on/off control signal output to the
µ
PC1330H (IC302)
70
A-HALF
I
Detection input from the deck-A half detect switch “L”: cassette in, “H”: no cassette
71
NC
—
Not used (fixed at “L”)
72
NC
—
Not used (fixed at “L”)
73
DISPLAY KEY
I
Display key input terminal S752 (DISPLAY)
74
POWER KEY
I
Power key input terminal S796 (I/1)
75
STBY LED
O
STANDBY LED on/off control signal output terminal “H”: LED on, “L”: LED off
76
NC
—
Not used (fixed at “L”)
77
NC
—
Not used (fixed at “L”)
78
GAME/VIDEO
O
Game/video selection signal output to the BU4052BCF (IC105)
“H”: game in, “L”: video in
“H”: game in, “L”: video in
79
DBFB ON/OFF
O
DBFB on/off control signal output terminal “H”: DBFB on, “L”: BDFB off
80
GEQ DATA
O
Data output for the graphic equalizer IC (IC101)
81
GEQ CLK
O
Clock output for the graphic equalizer IC (IC101)
82
LINE-MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
83
STK-MUTE
O
Muting on/off control signal output to the power AMP “H”: muting on
49
HCD-DX80
Pin No.
Pin Name
I/O
Description
84
STBY-RELAY
O
Standby relay on/off control signal output to the RY971 “H”: relay on
85
REAR-RELAY
O
Rear speaker relay on/off control signal output to the STA. AMP (TA-DX80) “H”: relay on
86
SURR-RELAY
O
Surround speaker relay on/off control signal output terminal “H”: relay on Not used (open)
87
FRONT-RELAY
O
Front speaker relay on/off control signal output to the RY801 “H”: relay on
88
PROTECT
I
Speaker protect signal input terminal “L”: protect on
89
A-SHUT
I
Shut off detection signal input from the deck-A side reel pulse detector
90
B-SHUT
I
Shut off detection signal input from the deck-B side reel pulse detector
91
B-HALF
I
Detection input from the deck-B half detect switch “L”: cassette in, “H”: no cassette
92
MODEL-IN
I
Model select signal input terminal
93
SPEC-IN
I
Version select signal input terminal
94
FREQ-B
O
Frequency control signal output to the Booster AMP (TA-DX80)
95
FREQ-A
O
Frequency control signal output to the Booster AMP (TA-DX80)
96
AVSS
—
Ground terminal (for analog)
97
BOOSTER-SW
I
Booster encoder signal input from the satellite AMP (TA-DX80)
98
VREF
—
Analog reference voltage terminal
99
AVCC
—
Power supply terminal (+5V) (for analog)
100
AC CUT
I
AC power off detection signal input from the reset signal generator (IC502)
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