Sony HCD-D90AV / HCD-GR10AV / HCD-RX100AV / MHC-D90AV / MHC-GR10AV / MHC-RX100AV Service Manual ▷ View online
— 81 —
• Power section
IC301 uPC1237HA
• Deck section
IC602 uPC1330HA
• CD motor section
IC701 M54641L
1
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3
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6
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9
10
TSD
CONTROL
LOGIC
PO WER
SAVE
GND
RIN
VREF
OUT2
OUT2
RNF
GND
VM
VCC
FIN
OUT1
IC801 BA6286N
1
2
3
4
5
6
7
8
OVER LOAD DET
F/F
OFFSET DET
LATCH/
AUTORESET
V
CC
ON
MUTE
AC OFF
DET
V
CC
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
1
5
2
7
3
6
4
POWER
AMP.
AMP.
POWER
AMP.
AMP.
CONTROL
INPUT
AMP.
INPUT
AMP.
REG
8
VCC
VCC
REFERENCE
OUT2
OUT1
IN1
IN2
GND
— 82 —
7-20. IC PIN FUNCTIONS
• IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR)
Pin No.
Pin Name
I/O
Function
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
TA M
TA O
SL P
SL M
SL O
ISET
V
CC
LOCK
CLK
XLT
DATA
XRST
C.OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
RF I
RF O
O
I
I
I
I
O
I
I
I
I
I
I
O
I
I
O
I
I
I
I
I
I
I
O
O
O
O
I
O
I
I
I
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Focus error amplifier output
Connected internally to the window comparator input for bias adjustment
Focus error input
Capacitor connection pin for defect time constant
Ground this pin through a capacitor for cutting the focus servo high-frequency gain
External time constant setting pin for boosting the focus servo low-frequency
Focus drive output
Focus amplifier inverted input
External time constant setting pin for generating focus search waveform
External time constant setting pin for switching tracking high-frequency gain
External time constant setting pin for switching tracking high-frequency gain
Peak frequency setting pin for focus and tracking phase compensation amplifier
Tracking amplifier inverted input
Tracking drive output
Sled amplifier non-inverted input
Sled amplifier inverted input
Sled drive output
Connect an external capacitance to set the current which determines the Focus search,
Track jump, and Sled kick heights
Positive power supply
The sled overrun prevention circuit operates when this pin is Low (No pull-up resistance)
Serial data transfer clock input from CPU (No pull-up resistance)
Lach input from CPU (No pull-up resistance)
Serial data input from CPU (No pull-up resistance)
Reset input; resets at Low (No pull-up resistance)
Track number count signal output
Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the com-
mand from CPU
Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from
CPU
Focus OK comparator output
Input for the defect bottom hold output with capacitance coupled
Defect bottom hold output
Connected internally to the interruption comparator input
Connection pin for defect bottom hold capacitor
Connection pin for MIRR hold capacitor
MIRR comparator non-inverted input
Input for the RF summing amplifier output with capacitance coupled
RF summing amplifier output
Eye-pattern check point
FZC
: Focus zero-cross
DFCT : Defect
TZC
TZC
: Tracking zero-cross
BALH : E-F Balance (High)
TGH
TGH
: Tracking Gain (High)
FOH
: Focus Bias (High)
ATSC : Anti Shock
MIRR : Mirror
BALL : E-F Balance (Low)
TGL
MIRR : Mirror
BALL : E-F Balance (Low)
TGL
: Tracking Gain (Low)
FOL
: Focus Bias (Low)
— 83 —
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45
46
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49
50
51
52
Pin No.
Pin Name
I/O
Function
RF M
RFTC
LD
PD
PD1
PD2
FE BIAS
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FZC
I
I
O
I
I
I
I
I
I
–
–
O
I
I
I
I
I
O
I
RF summing amplifier inverted input
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin
External time constant setting pin during RF level control
APC amplifier output
APC amplifier input
RF I-V amplifier inverted input
Connect these pins to the photo diode A+C and B+D pins
Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment
F I-V and E I-V amplifier inverted input
Connect these pins to photo diodes F and E
I-V amplifier E gain adjustment
(When not using automatic balance adjustment)
Negative power supply
Tracking error amplifier output
E-F signal is output
Comparator input for balance adjustment
(Input from TEO through LPF)
Tracking error input
Window comparator input for ATSC detection
Trackig zero-cross comparator input
Capacitor connection pin for defect time constant
(V
CC
+ V
EE
)/2 direct voltage output
Focus zero-cross comparator input
APC
: Auto Power Control
— 84 —
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
• IC103 DIGITAL SIGNAL PROCESSOR (CXD2519Q)
–
–
O
O
O
O
I
O
O
I
I
I
I
I
O
O
O
I
I
I
I
O
I
–
–
O
O
O
O
I
I
I
O
O
I
O
I
O
O
I
+5V power supply
Ground
Lch “L” detection flog (Not used)
Rch “L” detection flog (Not used)
Test output (Not used)
Master clock divider output (Not used)
Clock input for SQSO read out
Serial output for Sub-Q 80bit
SENS signal output to CPU
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS input from IC101
Numbers of track jump counted signal input
Serial data output to IC101
Serial data latch output to IC101
Serial data transfer clock output to IC101
Micro computer demodulation interface (Input A)
Micro computer demodulation interface (Input B)
Micro computer demodulation interface (Input C)
Micro computer demodulation interface (Input D)
Micro computer demodulation interface (Output)
Focus OK input
+5V power supply
Ground
Output to control ON/OFF of spindle motor (Not used)
Output to control spindle motor servo
Output to control spindle motor servo (Not used)
GFS is sampled by 460Hz
Input to control the outside spindle motor
Test pin (Connected to ground)
Test pin (Connected to ground)
Charge-pump output (Not used)
Charge-pump output (Not used)
VCO2 oscillator input (Not used)
VCO2 oscillator output (Not used)
VCO2 control voltage input
Charge-pump output to master PLL
Filter output to master PLL
Filter input for master PLL
VDD
VSS
LMUT
RMUT
ACDT
CKOUT
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
VDD
VSS
MON
MDP
MDS
LOCK
PWMI
TES0
TES1
VPCO2
VPCO1
VCKI
V16M
VCTL
PCO
FILO
FILI
GFS
: Guarded Frame Sync
PLL
: Phase Locked Loop
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