Sony DHC-MD313 / HCD-MD313 Service Manual ▷ View online
– 72 –
– MAIN Section –
IC570
IC570
LA5620
IC603
M62016L
1
–
+
12
DELAY
CIRCUIT
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
V
CC
ANA5
SYS3.3
BACK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
– 73 –
IC801
LB1641
IC1500
BU1922F
– AUDIO Section –
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
QUALITY BIT
GENERATOR
DEFFERENTIAL
DECODER
BIPHASE
SYMBOL
SYMBOL
DECODER
OSCILLATOR
AND
DIVIDER
57kHz
BANDPASS
(8th ORDER)
CONTAS LOOP
VARIABLE AND
FIXED DIVIDER
FIXED DIVIDER
REFERENCE
VOLTAGE
ANTI-
ALIASING
FILTER
CLOCKED
COMPARATOR
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
RECONSTRUCTION
FILTER
14
15
16
13
12
11
10
9
3
2
1
4
5
6
7
8
CLOCK REGENERATION
AND SYNC
VP1
RDCL
TS7
OSCO
OSCI
V
DDD
V
SSD
TEST
TSTL
D
QUAL
RDDA
Vref
MUX
V
DDA
V
SSA
CIN
SCOUT
– 74 –
6-12.
IC PIN FUNCTION DESCRIPTION
•
BD (MD) BOARD IC101
CXA2523AR (RF AMPLIFIER)
Pin No.
Pin Name
I/O
Function
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input terminal
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2652AR (IC121)
17
SCLK
I
Serial clock signal input from the CXD2652AR (IC121)
18
XLAT
I
Serial latch signal input from the CXD2652AR (IC121)
19
XSTBY
I
Standby signal input terminal
“L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input from
the CXD2652AR (IC121)
the CXD2652AR (IC121)
21
VREF
O
Reference voltage output terminal
Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2652AR (IC121)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2652AR (IC121)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz ± 1 kHz) output to the CXD2652AR (IC121)
33
AUX
O
Auxiliary signal (I3 signal/temperature signal) output to the CXD2652AR (IC121)
34
FE
O
Focus error signal output to the CXD2652AR (IC121)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2652AR (IC121)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC121)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC121)
38
RF
O
Playback EFM RF signal output to the CXD2652AR (IC121)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal
Not used (open)
42
COMPP
I
User comparator input terminal
Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal
Not used (open)
45
OPN
I
User operational amplifier inversion input terminal
Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
– 75 –
•
BD (MD) BOARD IC121
CXD2652AR
•
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK
•
PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Pin No.
Pin Name
I/O
Function
1
MNT0 (FOK)
O
Focus OK signal output to the MD system controller (IC316)
“H” is output when focus is on
2
MNT1 (SHCK)
O
Track jump detection signal output to the MD system controller (IC316)
3
MNT2 (XBUSY)
O
Monitor 2 signal output to the MD system controller (IC316)
4
MNT3 (SLOC)
O
Monitor 3 signal output to the MD system controller (IC316)
5
SWDT
I
Writing data signal input from the MD system controller (IC316)
6
SCLK
I
Serial clock signal input from the MD system controller (IC316)
7
XLAT
I
Serial latch signal input from the MD system controller (IC316)
8
SRDT
O (3)
Reading data signal output to the MD system controller (IC316)
9
SENS
O (3)
Internal status (SENSE) output to the MD system controller (IC316)
10
XRST
I
Reset signal input from the MD system controller (IC316)
“L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD system controller (IC316)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD system controller (IC316)
“L” is output every 13.3 msec
“L” is output every 13.3 msec
Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD system controller (IC316)
“H”: recording mode, “L”: playback mode
“H”: recording mode, “L”: playback mode
14
XINT
O
Interrupt status output to the MD system controller (IC316)
15
TX
I
Recording data output enable signal input from the MD system controller (IC316)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input terminal
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode (for optical in)
22
DOUT
O
Digital audio signal output terminal when playback mode (for optical out)
Not used
23
ADDT
I
Recording data input from the A/D, D/A converter (IC201)
24
DADT
O
Playback data output to the A/D, D/A converter (IC201)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)
26
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201)
27
FS256
O
Clock signal (11.2896 MHz) output to the A/D, D/A converter (IC201)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29
A03
O
30
A02
O
31
A01
O
32
A00
O
33
A10
O
34
A04
O
Address signal output to the external D-RAM (IC124)
35
A05
O
36
A06
O
37
A07
O
38
A08
O
39
A11
O
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
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