Sony DHC-FL5D / HCD-FL5D Service Manual ▷ View online
105
HCD-FL5D
•
MC BOARD IC101 M30622MGN-B06FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61520FP
2
AMP-CLK
O
Serial data transfer clock signal output to the M61520FP
3
AMP-LAT
O
Serial data latch pulse signal output to the M61520FP
4
SIRCS
I
Remote control signal input from the remote control receiver
5
DIG-TX
O
Serial data output to the audio digital signal processor and digital audio interface receiver
6
DSP-RX
I
Serial data input from the digital audio interface receiver
7
DIG-CLK
O
Serial data transfer clock signal output to the audio digital signal processor and
digital audio interface receiver
digital audio interface receiver
8
GND
—
Ground terminal
9
GND
—
Not used
10
XC-IN
I
Sub system clock input terminal (32.768 kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal input terminal Not used
19
SCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used
20
DIR-INT
O
Interrupt request signal output to the digital audio interface receiver
21
CAPM-H/L
O
High/normal speed selection signal output of the capstan motor
“L”: high speed, “H”: normal speed
“L”: high speed, “H”: normal speed
22
CAPM-CNT1
O
Capstan motor drive signal output
23
A TRG
O
Deck-A side trigger plunger drive signal output “H”: plunger on
24
BU-PWM3
O
RFDC PWM signal output terminal Not used
25
B TRG
O
Deck-B side trigger plunger drive signal output “H”: plunger on
26
BU-PWM2
O
PWM signal output terminal Not used
27
A-HALF
I
Deck-A cassette detection signal input terminal “L”: no cassette, “H”: cassette in
28
BU-PWM1
O
Focus servo drive PWM signal output terminal Not used
29
IIC-CLK
I/O
IIC data reading clock signal input or transfer clock signal output with the fuluorescent indicator
driver and DVD system processor
driver and DVD system processor
30
IIC-DATA
I/O
IIC two-way data bus with the fuluorescent indicator driver
31
CAN'T USE
I
Not used
32
SQ-DATA-IN
I
Subcode Q data input terminal Not used
33
SQ-CLK
O
Subcode Q data reading clock signal output terminal Not used
34
SENS
I
Internal status detection monitor input terminal Not used
35
CD-DATA
O
Serial data output terminal Not used
36
CAN'T USE
I
Not used
37
CD-CLK
O
Serial data transfer clock signal output terminal Not used
38
POWER LED
O
LED drive signal output terminal
39
CLOCK-OUT
O
Clock (32.768 kHz) signal output terminal (for test mode) Not used
40
LDON(3STATE)
O
Laser diode on/off control signal output terminal Not used
41
M-RESET
I
Reset signal output to the fluorescent indicator tube driver and front panel controller
106
HCD-FL5D
Pin No.
Pin Name
I/O
Description
42
XLT
O
Serial data latch pulse output terminal Not used
43
XRST
O
Reset signal output to the DVD system processor “L”: reset
44, 45
VIDEO-MUTE,
VIDEO-MUTE2
O
Video muting on/off control signal output terminal “L”: muting on
46
NO-USE
—
Not used
47, 48
VOLUME A,
VOLUME B
I
Rotary encoder pulse input terminal
49
A PLAY
I
Deck-A play detection signal input terminal “H”: deck-A play
50
B PLAY
I
Deck-B play detection signal input terminal “H”: deck-B play
51
NO-USE
—
Not used
52
RDS-DATA
I
Serial data input terminal Not used
53
ST MUTE
O
Tuner muting on/off control signal output to the FM/AM tuner unit
54
STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
55
TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
56
ST CE
O
PLL serial chip enable signal output to the tuner unit
57
ST DOUT
O
PLL serial data output to the tuner unit
58
ST DIN
I
PLL serial data input from the tuner unit
59
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
60
LINE MUTE
O
Line muting on/off control signal output “H”: muting on
61
DIR-CS
O
Chip enable signal output to the digital audio interface receiver
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT-TEST
O
Output terminal for the software test
64
VSS
—
Ground terminal
65
DIR-RX
I
Read data input from the digital audio interface receiver
66
DAC-LAT
O
Serial data latch pulse signal output to the D/A converter
67
DSP-ACK
I
Acknowledge signal input from the audio digital signal processor
68
DSP-CS
O
Chip select signal output to the audio digital signal processor
69
DSP-DECODE
I
Decode signal input from the audio digital signal processor
70
BTL 2.1CH D
O
BTL 2.1ch switching signal output terminal
71
BTL 2.1CH C
O
BTL 2.1ch switching signal output terminal
72
BTL 2.1CH B
O
BTL 2.1ch switching signal output terminal
73
DISPLAY KEY
I
Key input terminal (A/D input)
74
POWER KEY
I
Key input terminal (A/D input)
75
DIR-UNLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
76
BTL 2.1CH A
O
BTL 2.1ch switching signal output terminal
77
PROTECT
O
Speaker output over load detection signal input “L”: over load
78
FAN-CTRL
O
Fan motor drive signal output
79
CD-POWER
O
Power on/off control signal output for the CD/DVD section “H”: power on
80
STK-MUTE
O
Power amplifier on/off control signal output “L”: standby mode, “H”: power amplifier on
81
BIAS
O
Recording bias on/off control signal output “H”: bias on
82
TC-RELAY
O
Recording/playback selection signal output “L”: playback, “H”: recording
83
STBY-RELAY
O
Main power on/off control signal output “H”: power on
84
REC-MUTE
O
Recording muting on/off selection signal output terminal “L”: muting on
85
TC-MUTE
O
Playback muting on/off control signal output “H”: muting on
86
PB-A/B
O
Deck-A/B selection signal output “L”: deck-B, “H”: deck-A
87
EQ-H/N
O
Normal/high speed selection signal output “L”: normal speed, “H”: high speed
107
HCD-FL5D
Pin No.
Pin Name
I/O
Description
88
ALC
O
Automatic limiter control signal output “H”: limiter on
89
DIR-RST
O
Reset signal output to the digital audio interface receiver
90
S/W
O
SW phase control signal output terminal
91
A-SHUT
I
Shut off detection signal input from the deck-A side reel pulse detector
92
B-SHUT
I
Shut off detection signal input from the deck-B side reel pulse detector
93
B-HALF
I
Deck-B cassette detection signal input terminal “L”: cassette in, “H”: no cassette
94
MODEL-IN
I
Model setting terminal
95
SPEC-IN
I
Destination setting terminal
96
AVSS
—
Ground terminal
97
AMS-IN
I
Automatic music sensor detection signal input
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVCC
—
Power supply terminal (+3.3V)
100
AC-CUT
I
AC cut on/off detection signal input from the reset signal generator
“L”: AC cut on, “H”: AC cut off or checked
“L”: AC cut on, “H”: AC cut off or checked
108
HCD-FL5D
•
DSP BOARD IC601 CXD9720Q (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the digital audio interface receiver “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
5
VDDI
—
Power supply terminal (+3.3V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13 MHz)
10
VDDI
—
Power supply terminal (+3.3V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13 MHz)
13
MS
I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
18
SDI1
I
Audio serial data input from the digital audio interface receiver
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the A/D converter or digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
GP12
O
Clock signal output terminal Not used
38
GP13
O
Clock enable signal output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+3.3V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
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