Sony DHC-FL3 / HCD-FL3 Service Manual ▷ View online
73
HCD-FL3
– DSP Board –
IC603
LC89057W-VF4-E
38
37
36
23
24
1
2
3
4
5
44
8
9
10
46
17
22
21
20
30
35
25
26
27
28
29
32
33
34
16
45
13 14 15
47
40
41
48
DI
39
CE
DO
RERR
SLRCK
SDIN
RXOUT
RX0
RX1
RX2
RX3
6
DGND
7
DVDD
11
DVDD
12
DGND
TMCK/PIO
RX4
RX5/V1
RX6/U1
TLRCK/PIO2
RBCK
18
DGND
19
DVDD
SBCK
RDATA
RLRCK
DVDD
31 DGND
INT
DGND
DVDD
XMCK
XOUT
XIN
EMPHA/UO
AUDIO/VO
CKST
RMCK
TBCK/PIO1
LPF
AVDD
AGND
TDATA/PIO3
CL
XMODE
42
DGND
43
DVDD
TXO/PIOEN
MICROCONTROLLER
INTERFACE
DATA
SELECTOR
CLOCK
SELECTOR
INPUT
SELECTOR
DATA
DEMODULATOR
&
LOCK DETECT
MODULATOR
&
PARALLEL PORT
PLL
1/N
C bit,
U bit
IC611
PCM1800E/2K
SINGLE-END
DEFERENTIAL
CONVERTER
REFERENCE
SINGLE-END
DEFERENTIAL
CONVERTER
DIGITAL ∑
MODULATOR
DIGITAL ∑
MODULATOR
1/64
DECIMATION
FILTER
&
LOW-CUT
FILTER
CLOCK/
TIMING CONTROL RESET/
POWER CONTROL
SERIAL I/O
INTERFACE
&
MODE/FORMAT
CONTROL
LIN
V REF 1
REFCOM
V REF 2
RIN
RSTB
FMT0
BYPASS
FMT1
MODE1
MODE0
FSYNC
1
2
3
4
5
6
8
7
9
11
10
12
AGND
VCC
C PR
C NR
C PR
C NR
DGND
SYSCL
K
DOUT
BCK
LRCK
VDD
24
23
22
21
20
19
17
16
15 14 13
18
74
HCD-FL3
IC612
PCM1608Y/2K
SYSTEM
CLOCK
MANAGER
FUNCTION
CONTROL
INTERFACE
SERIAL
INPUT
INTERFACE
4X/8X
OVER SAMPLING
DIGITAL
FILTER
WITH
FUNCTION
CONTROLLER
ENHANCED
MULTI-
LEVEL
DELTA-
SIGMA
MOJULE
ZERO DETECT
DAC
LPF
DAC
LPF
DAC
LPF
DAC
LPF
DAC
LPF
DAC
LPF
DAC
LPF
DAC
LPF
RST
SCKI
SCKO
BCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
LRCK
37
38
39
40
42
43
44
45
46
47
48
41
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
1
2
3
4
5
6
7
8
9
10
11
12
VOUT2
VOUT1
VCOM
VOUT7
AGND5
VCC5
AGND6
VOUT8
AGND4
VCC4
AGND3
VCC3
13
14
15
16
17
18
19
20
21
22
23
24
ML
MC
MDI
MDO
ZERO8
DATA4
ZERO7
NC
VCC1
AGND1
VCC2
AGND2
36 35 34 33
32 31 30
29
28
27
26
25
75
HCD-FL3
8-42.
IC PIN FUNCTION DESCRIPTION
•
MC BOARD IC101 M30622MGN-A06FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61520FP
2
AMP-CLK
O
Serial data transfer clock signal output to the M61520FP
3
AMP-LAT
O
Serial data latch pulse signal output to the M61520FP
4
SIRCS
I
Remote control signal input from the remote control receiver
5
DIG-TX
O
Serial data output to the audio digital signal processor and digital audio interface receiver
6
DSP-RX
I
Serial data input from the digital audio interface receiver
7
DIG-CLK
O
Serial data transfer clock signal output to the audio digital signal processor and
digital audio interface receiver
digital audio interface receiver
8
GND
—
Ground terminal
9
GND
—
Not used
10
XC-IN
I
Sub system clock input terminal (32.768 kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal input from the RDS decoder on the tuner unit
19
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2587Q
20
DIR-INT
O
Interrupt request signal output to the digital audio interface receiver
21
CAPM-H/L
O
High/normal speed selection signal output of the capstan motor
“L”: high speed, “H”: normal speed
“L”: high speed, “H”: normal speed
22
CAPM-CNT1
O
Capstan motor drive signal output
23
A TRG
O
Deck-A side trigger plunger drive signal output “H”: plunger on
24
BU-PWM3
O
RFDC PWM signal output to the RF amplifier
25
B TRG
O
Deck-B side trigger plunger drive signal output “H”: plunger on
26
BU-PWM2
O
PWM signal output to the RF amplifier
27
A-HALF
I
Deck-A cassette detection signal input terminal “L”: no cassette, “H”: cassette in
28
BU-PWM1
O
Focus servo drive PWM signal output to the RF amplifier
29
IIC CLOCK
O
IIC data reading clock signal output to the fuluorescent indicator driver
30
IIC DATA
I/O
IIC two-way data bus with the fuluorescent indicator driver
31
CAN'T USE
I
Not used
32
SQ-DATA-IN
I
Subcode Q data input from the digital signal processor
33
SQ-CLK
O
Subcode Q data reading clock signal output to the digital signal processor
34
SENS
I
Internal status detection monitor input from the digital signal processor
35
CD-DATA
O
Serial data output to the digital signal processor
36
CAN'T USE
I
Not used
37
CD-CLK
O
Serial data transfer clock signal output to the digital signal processor
38
POWER LED
O
LED drive signal output terminal
39
CLOCK-OUT
O
Clock (32.768 kHz) signal output terminal (for test mode) Not used
40
LDON(3STATE)
O
Laser diode on/off control signal output to the RF amplifier “L”: laser diode on
41
M-RESET
I
Reset signal output to the fluorescent indicator tube driver and led drive controller
42
XLT
O
Serial data latch pulse output to the digital signal processor
76
HCD-FL3
Pin No.
Pin Name
I/O
Description
43
XRST
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
44
V-MUTE
O
Video muting on/off control signal output terminal “L”: muting on Not used
45
CD-MUTE
O
CD analog signal muting on/off control signal output “H”: muting on
46
NO-USE
—
Not used
47, 48
VOLUME A,
VOLUME B
I
Rotary encoder pulse input terminal
49
A PLAY
I
Deck-A play detection signal input terminal “H”: deck-A play
50
B PLAY
I
Deck-B play detection signal input terminal “H”: deck-B play
51
NO-USE
—
Not used
52
RDS-DATA
I
Serial data input terminal Not used
53
ST MUTE
O
Tuner muting on/off control signal output to the FM/AM tuner unit
54
STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
55
TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
56
ST CE
O
PLL serial chip enable signal output to the tuner unit
57
ST DOUT
O
PLL serial data output to the tuner unit
58
ST DIN
I
PLL serial data input from the tuner unit
59
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
60
LINE MUTE
O
Line muting on/off control signal output “H”: muting on
61
DIR-CS
O
Chip enable signal output to the digital audio interface receiver
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT-TEST
O
Output terminal for the software test
64
VSS
—
Ground terminal
65
DIR-RX
I
Read data input from the digital audio interface receiver
66
DAC-LAT
O
Serial data latch pulse signal output to the D/A converter
67
DSP-ACK
I
Acknowledge signal input from the audio digital signal processor
68
DSP-CS
O
Chip select signal output to the audio digital signal processor
69
DSP-DECODE
I
Decode signal input from the audio digital signal processor
70
BTL 2.1CH D
O
BTL 2.1ch switching signal output terminal
71
BTL 2.1CH C
O
BTL 2.1ch switching signal output terminal
72
BTL 2.1CH B
O
BTL 2.1ch switching signal output terminal
73
DISPLAY KEY
I
Key input terminal (A/D input)
74
POWER KEY
I
Key input terminal (A/D input)
75
DIR-UNLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
76
BTL 2.1CH A
O
BTL 2.1ch switching signal output terminal
77
PROTECT
O
Speaker output over load detection signal input “L”: over load
78
FAN-CTRL
O
Fan motor drive signal output
79
CD-POWER
O
Power on/off control signal output for the CD section “H”: power on
80
STK-MUTE
O
Power amplifier on/off control signal output “L”: standby mode, “H”: power amplifier on
81
BIAS
O
Recording bias on/off control signal output “H”: bias on
82
TC-RELAY
O
Recording/playback selection signal output “L”: playback, “H”: recording
83
STBY-RELAY
O
Main power on/off control signal output “H”: power on
84
REC-MUTE
O
Recording muting on/off selection signal output terminal “L”: muting on
85
TC-MUTE
O
Playback muting on/off control signal output “H”: muting on
86
PB-A/B
O
Deck-A/B selection signal output “L”: deck-B, “H”: deck-A
87
EQ-H/N
O
Normal/high speed selection signal output “L”: normal speed, “H”: high speed
88
ALC
O
Automatic limiter control signal output “H”: limiter on
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