DOWNLOAD Sony DAV-TZ100 / DAV-TZ200 / DAV-TZ300 / HCD-TZ100 / HCD-TZ200 / HCD-TZ300 Service Manual ↓ Size: 3.31 MB | Pages: 70 in PDF or view online for FREE

Model
DAV-TZ100 DAV-TZ200 DAV-TZ300 HCD-TZ100 HCD-TZ200 HCD-TZ300
Pages
70
Size
3.31 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
dav-tz100-dav-tz200-dav-tz300-hcd-tz100-hcd-tz200-.pdf
Date
PREV: Sony STR-DN1000 (serv.man2) Service Manual

Sony DAV-TZ100 / DAV-TZ200 / DAV-TZ300 / HCD-TZ100 / HCD-TZ200 / HCD-TZ300 Service Manual ▷ View online

HCD-TZ100/TZ200/TZ300
45
IC3000  CXD9965TN (MAIN Board (7/8))
IC3002  CXD9965TN (MAIN Board (7/8))
IC3004  CXD9965TN (MAIN Board (8/8))
1
2
3
4
5
6
INTERNAL PULLUP
RESISTORS TO VREG
PROTECTION
AND
I/O LOGIC
OVERLOAD
PROTECTION
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
44
43
42
41
40
39
38
37
35
27
16
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
26
33
34
32
31
30
8
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
29
24
25
23
36
18
19
20
21
22
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
27
28
POWER
ON
RESET
TEMP.
SENSE
UNDER-
VOLTAGE
PROTECTION
4
VREG
I-SENSE
13
14
15
17
12
7
11
9
10
M3
M2
M1
PWM_C
/RESET_CD
GVDD_B
/DTW
NC
NC
/SD
PWM_A
/RESET_AB
GND
AGND
VREF
PWM_B
OC_ADJ
PWM_D
NC
NC
VDD
GVDD_C
NC
BST_D
GVDD_D
OUT_D
PVDD_D
PVDD_D
GND_C
GND_D
BST_C
PVDD_C
OUT_C
OUT_B
PVDD_B
BST_B
OUT_B
GND_B
PVDD_A
PVDD_A
OUT_A
GVDD_A
BST_A
NC
4
HCD-TZ100/TZ200/TZ300
46
IC901  STR-F6138-LF1352 (POWER Board) (MX model)
IC901  STR-F6168-LF1352 (POWER Board) (EXCEPT MX model)
OCP/INH
1
GND
2
D
3
VCC
4
FB/OLP
5
+ 
–
+ 
–
+
–
+
–
+ 
–
Delay
OVP
TSD
Delay
Reg2
Reg1
Reg3
Current mirror
POWER
MOS FET
Latch
OSC
Boottom Skip
Logic
OCP2
Logic
Internal
Bias
OCP1
Vocp
Rg3
Rg2
Rg1
OCP2
+
–
UVL0
ON=16V
OFF=10.5V
INH1
INH2
FB
Vth1
+
–
IOLP
Volp
Vth2
Vocp(BSIN,OUT)
HCD-TZ100/TZ200/TZ300
47
•  IC Pin Function Description
MAIN  BOARD (2/8)  IC1101  CXD9917R-A
(CD/DVD RF AMP, FOCUS/TRACKING ERROR AMP, DVD SYSTEM CONTROL, DPS, USB CONTROL)
Pin No.
Pin Name
I/O
Description
1
OSN
—
RF offset cancellation capacitor connecting terminal
2
RFGC
I
RF AGC loop capacitor connecting terminal
3
IREF
I
Current reference setting terminal
4
AVDD3
—
Power supply (VDD3.3V)
5
AGND
—
Ground
6
DVDA
I
AC coupled input path A
7
DVDB
I
AC coupled input path B
8
DVDC
I
AC coupled input path C
9
DVDD
I
AC coupled input path D
10
DVDRFIP
I
DC coupled DVD RF signal input RFIP
11
MA
I
DC coupled main-beam RF signal input A
12
MB
I
DC coupled main-beam RF signal input B
13
MC
I
DC coupled main-beam RF signal input C
14
MD
I
DC coupled main-beam RF signal input D
15
SA
—
Not used (Open)
16
SB
—
Not used (Open)
17
TNI
I
DC coupled main-beam RF signal input E
18
TPI
I
DC coupled main-beam RF signal input F
19
MDI1
I
Laser power monitor input
20
MDI2
I
Laser power monitor input
21
LDO2
O
Laser diode (DVD) drive signal output
22
LDO1
O
Laser diode (CD) drive signal output
23
SVDD3
—
Power supply (RF+3.3V)
24
CSO
O
Not used (Open)
25
RFLVL
O
RFRP low pass output
26
SGND
—
Ground
27
V2REFO (2.8V)
O
Reference voltage (2.8V) output
28
V20 (2.0V)
O
Reference voltage (2.0V) output
29
VREFO (1.4V)
O
Reference voltage (1.4V) output
30
FEO
O
Focus error monitor output
31
TEO
O
Tracking error monitor output
32
TEZISLV
O
TE Slicing Level input
33
OP_OUT
O
Op amp output
34
OP_INN
I
Op amp negative input
35
OP_INP
I
Spindle feedback signal input
36
DMO
O
Spindle motor control PWM signal output
37
FMO
O
Sled motor control PWM signal output
38
TROPENPWM
O
Tray Loading motor PWM signal output
39
IOPMON
I
Iop Monitor input
40
TRO
O
Tracking servo control signal output
41
FOO
O
Focus servo control signal output
42
AGND18
—
Ground
43
AVDD18
—
Power supply (+1.8V)
44
USB_DP
I/O
USB port serial data input/output
45
USB_DM
I/O
USB port serial data input/output
46
USB_VDD3
—
USB power supply (+3.3V)
47
USB_VSS
—
USB ground
48
PAD_VRT
—
Not used
49
USB_VDD18
—
Power supply (+1.8V)
50
USB_VSS
I
Ground
51
DIR_ERROR/NC
I
DIR PLL error signal input
52
DIR_AUDIO/NC
I
DIR audio signal input
53
LIMITSW
I
LIMIT SW signal input
54
MSW
O
DVD/CD PD –VR select signal output
55
DVDD18
—
Power supply (+1.8V)
56 to 62
HA2 to HA8
O
Flash ROM address bus A2 to A8 output
HCD-TZ100/TZ200/TZ300
48
Pin No.
Pin Name
I/O
Description
63, 64
HA18, HA19
O
Flash ROM address bus A18, A19 output
65
DVDD3
—
Power supply (+3.3V)
66
XWR
O
Flash ROM write signal output
67 to 74
HA16 to HA9
O
Flash ROM address bus A16 to A9 output
75
HA20
Flash ROM address bus A20 output
76
XROMCS
O
Flash ROM chip select signal output
77
HA1
O
Flash ROM address bus A1 output
78
XRD
O
Flash ROM read signal output
79, 80
HD0, HD1
I/O
Flash ROM data bus D0, D1 input/output
81
DVSS
—
Ground
82 to 86
HD2 to HD6
I/O
Flash ROM data bus D2 to D6 input/output
87
HA21
I/O
Flash ROM data bus D21 input/output
88
RESERVED
—
Not used (Open)
89
HD7
I/O
Flash ROM data bus D7 input/output
90
DVSS
—
Ground
91, 92
HA17, HA0
O
Flash ROM address bus A17, A0 output
93
DVDD18
O
Flash ROM data bus D18 input/output
94
FWD
O
Tray loading motor control (FWR) signal output
95
REV
O
Tray loading motor control (REV) signal output
96
DVDD3
—
Power supply (+3.3V)
97
IFSDO
O
CPU I/F serial data output
98
IFCK
O
CPU I/F serial clock output
99
xIFCS
O
CPU I/F chip select output
100
IFSDI
I
CPU I/F serial data input
101
SCL
O
EEPROM serial clock output
102
SDA
I/O
EEPROM serial data input/output
103
CKSW
I
Chuck/Tray detect switch signal input
104
OCSW
I
Chuck/Tray detect switch signal input
105
RXD
I
RXD signal input from service connector
106
TXD
O
TXD signal output to service connector
107
ICE
O
Not used (Open)
108
xSYSRST
I
System reset signal input
109
RESERVED
I
Not used (Open)
110
xIFBSY
I
Busy signal  input from CPU I/F
111
DQM0
O
SDRAM lower byte mask signal output
112
EEWP
O
EEPROM ready/Busy wake up signal output
113 to 117
RD7 to RD3
I/O
SDROM data bus D7 to D3 input/output
118
DVDD3
—
Power supply (+3.3V)
119 to 121
RD2 to RD0
I/O
SDROM data bus D2 to D0 input/output
122 to 129
RD15 to RD8
I/O
SDROM data bus D15 to D8 input/output
130
TSD_M
I
TSD signal input
131
DVDD3
—
Power supply (+3.3V)
132
DQM1
O
SDRAM lower byte mask signal output
133
_RWE
O
SDRAM write enable signal output
134
_CAS
O
SDRAM column address strobe signal output
135
_RAS
O
SDRAM row address strobe signal output
136
_RCS
O
SDRAM chip select signal output
137, 138
BA0, BA1
O
SDRAM bank address 0, 1 output
139
RA10
O
SDRAM address bus A10 output
140, 141
RA0, RA1
O
SDRAM address bus A0, A1 output
142
DVDD18
—
Power supply (+1.8V)
143, 144
RA2, RA3
O
SDRAM address bus A0, A3 output
145
DVDD3
—
Power supply (+3.3V)
146
DRCLK
O
SDRAM clock output
147
CKE
O
SDRAM clock enable signal output
148
DVSS
—
Ground
149
RA11
O
SDRAM address bus A11 output
150 to 155
RA9 to RA4
O
SDRAM address bus A9 to A4 output
156
DVDD3
—
Power supply (+3.3V)
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