Sony DAV-S500 / DAV-S800 / HCD-S800 Service Manual ▷ View online
65
HCD-S500/S800
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
I/O
I
–
I
I
I
I
I
–
O
O
O
I/O
O
O
–
I/O
I/O
I/O
I/O
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
I
–
–
I
–
I
–
I
–
I
I
I
I
O
I
I
O
O
O
Description
ADC reference
Digital Ground
Test terminal L
DSP reset
Reset
Digital Ground
CLV speed error
Motor on
CLV phase error
Defect detection output
Jitter PWM output
EFM lock detection
Digital power supply 1.8V
GIO/external interruption
Digital power supply 3.3V
GIO/PGREF input
GIO/PGIN input
GIO/serial data in
GIO/serial data out
GIO/serial clock
GIO/FGREF input
GIO/FGIN input
GIO/Timer 2 clock input
GIO(input and output)
Digital Ground
Clock input
Analog Ground
Analog power supply
Defect input
Digital Ground
Clock for ECC 33MHz
Digital power supply 1.8V
System clock
Digital Ground
JTAG Boundary scan
TZC input
MIRR input
PWM output
Pin Name
VRTA
VSS
TESTK0
TESTK1
TESTK2
XDSPRST
XARPRST
VSS
MDS0
MON
MDP0
DFCT
JITPWM
LOCK
VDD1 1.8V
GIO0/INT2
GIO1/INT3
GIO2/INT4
GIO3/INT5
VDD 3.3V
GIO4/PGREF
GIO5/PGIN
GIO6/SDI
GIO7/SDO
GIO8/SCK
GIO9/FGREF
GIO10/FGIN
GIO11/TMC2
GIO12
GIO13
VSS
CLKIN
VSSA5
VDDA5 1.8V
DFCTI
VSS
MCKI
VDD 1.8V
SCKI
VSS
TRST
TMS
TDI
TCK
TDO
TZC
MIRR
PWM0
PWM1
PWM2
66
HCD-S500/S800
Pin No.
201
202
203
204
205
206
207
208
I/O
–
O
O
O
O
–
I
I
Description
Digital power supply 3.3V
PDM output
Digital Ground
CPU light
CPU lead
Pin Name
VDD 3.3V
PDM0
PDM1
PDM2
PDM3
VSS
XWR
XRD
67
HCD-S500/S800
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 to 25
26
27
28
29
30
31
32 to 34
35
36
37
38 to 41
42
43, 44
45
46, 47
48
49
50
51, 52
53
54
55, 56
57
58
59
60
61
62
63
64
65
66
I/O
–
I
I
I
–
O
O
O
I
I
I
–
O
O
O
O
–
O
I
I
–
O
I
I
I
–
O
O
O
–
O
–
O
O
–
O
I
O
–
O
I
–
I
O
I
O
O
O
O
O
Pin Name
VSCA0
XMSLAT
MSCK
MSDATI
VDCA0
MSDATO
MSREADY
XMSDOE
XRST
SMUTE
MCKI
VSIOA0
EXCKO1
EXCKO2
LRCK
F75HZ
VDIOA0
MNT0 - 7
TCK
TDI
VSCA1
TDO
TMS
TRST
TEST1 - 3
VDCA1
UBIT
XBIT
SUPDT0 - 3
VSIOA1
SUPDT4 - 5
VDIOA1
SUPDT6 - 7
SUPEN
VSCA2
NC
TEST4 - 5
NC
VDCA2
NC
BCKASL
VXDSD0
BCKAI
BCKAO
PHREFI
PHREFO
ZDFL
DSAL
ZDFR
DSAR
Description
Ground
Latch signal input for micom serial communication
Shift clock input for micom serial communication
Data input for micom serial communication
Power supply
Data output for micom serial communication
Output ready flag output for micom serial communication
Output enable signal output for micom serial communication
Reset signal input
Soft mute signal input (H:soft mute, L:off)
Master clock input (768Fs 33.8688MHz)
Ground for I/O
External clock output 1
External clock output 2 (not used)
Clock output (1Fs 44.1kHz)(not used)
Frame signal output
Power supply for I/O
Monitor signal output (not used)
Test clock input (connected to ground)
Input terminal for test
Ground
Output terminal for test (open)
Input terminal for test (open)
Reset terminal for test (open)
Input terminal for test (connected to ground)
Power supply
Output terminal for test (open)
DST monitor terminal (open)
Supplementary data output (open)
Ground for I/O
Supplementary data output (open)
Power supply for I/O
Supplementary data output (open)
Supplementary data acknoledge output (open)
Ground
Output terminal for test (open)
Input terminal for test (connected to ground)
Output terminal for test (open)
Power supply
Output terminal for test (open)
Bit clock I/O selection signal input for DSD data output (L:slave, H:master)
Ground for DSD data output
Bit clock input for DSD data output (open)
Bit clock output for DSD data output
Phase reference signal input for DSD signal phase modulation (open)
Phase reference signal output for DSD signal phase modulation (open)
Lch zero data detection flag signal output (open)
Lch DSD data output
Rch zero data detection flag signal output (open)
Rch DSD data output
• IC801
CXD2752R (PLAYBACK SIGNAL PROCESSOR) (DVD BOARD)
68
HCD-S500/S800
Pin No.
67
68
69
70
71
72
73
74
75
76
77
78, 79
80
81, 82
83
84, 85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101 to 105
106
107 to 109
110
111 to 114
115
116
117 to 120
121
122
123
124 to 125
126
127
128 to 129
130
131 to 134
135
136 to 139
I/O
–
O
O
O
O
–
O
O
O
O
–
O
–
O
–
O
–
O
I
I
–
O
O
O
–
I
I
I
O
–
I
I
–
I
–
I
–
–
I
–
I
I
–
I
I
–
–
I/O
–
I/O
Pin Name
VDDSD0
ZDFC
DSAC
ZDFLFE
DSALFE
VSDSD1
ZDFLS
DSALS
ZDFRS
DSARS
VDDSD1
IOUT0 - 1
VSCB0
IOUT2 - 3
VDCB0
IOUT4 -5
VSIOB0
IANCO
IFULL
IEMPTY
VDIOB0
IFRM
IOUTE
IBCK
VSCB1
IERR
IANCI
IPLAN
IHOLD
VDCB1
IVLD
IDIN0 - 4
VSIOB1
IDIN5 -7
VDIOB1
WAD0 - 3
TESTI
VSCB2
WAD4 - 7
VDCB2
WRFD
WCK
WAVDD0 - 1
WARFI
WAVRB
WAVSS1 - 0
VSIOA2
DQ7 - 4
VDIOA2
DQ3 - 0
Description
Power supply for DSD data output
Cch zero data detection flag signal output (open)
Cch DSD data output
LFEch zero data detection flag signal output (open)
LFEch DSD data output
Ground for DSD data output
LSch zero data detection flag signal output (open)
LSch DSD data output
RSch zero data detection flag signal output (open)
RSch DSD data output
Power supply for DSD data output
Output terminal for test (open)
Ground
Output terminal for test (open)
Power supply
Output terminal for test (open)
Ground for I/O
Output terminal for test (open)
Input teminal for test (connected to ground)
Input teminal for test (connected to ground)
Power supply for I/O
Output terminal for test (open)
Output terminal for test (open)
Output terminal for test (open)
Ground
Input teminal for test (connected to Vdd)
Input teminal for test (connected to ground)
Input teminal for test (connected to Vdd)
Output terminal for test (open)
Power supply
Input teminal for test (connected to ground)
Input teminal for test (connected to ground)
Ground for I/O
Input teminal for test (connected to ground)
Power supply for I/O
External A/D data input for PSP physical disc mark detection
Input teminal for test (pull-down)
Ground
External A/D data input for PSP physical disc mark detection
Power supply
Input teminal for test (connected to ground)
Clock input for PSP physical disc mark detection
A/D power supply for PSP physical disc mark detection (+2.5v)
Analog RF signal input for PSP physical disc mark detection
A/D bottom reference input for PSP physical disc mark detection
A/D ground for PSP physical disc mark detection
Ground for I/O
SDRAM data input/output terminal
Power supply for I/O
SDRAM data input/output terminal
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