Sony DAV-LF1 / SA-WSLF1 Service Manual ▷ View online
33
SA-WSLF1
IC503, 505 MC14052BDR2
IC519 LC89056W-E
38
37
36
23
24
1
2 3
4
5
44
8 9 10
46
17
22
21
20
30
35
25
26
27
28
29
32
33
34
16
45
13
14
15
47
40
41
48
CL
39
XSEL
CE
DI
EMPHA
AUDIO
DISEL
DOUT
DINO
DINI
DIN2
6
DGND
7
DVDD
11
AVDD
12
AGND
DOSEL0
R
VIN
LPF
CKSEL0
XSTATE
18 DGND
19 DVDD
XIN
XOUT
XMCK
DVDD
31
DGND
DO
CSFLAG
F0/P0/C0
F1/P1/C1
F2/P2/C2
VF/P3/C3
AUTO
BPSYNC
ERROR
DATAO
DOSEL1
CKOUT
BCK
LRCK
CKSEL1
MODE0
MODE1
42
DGND
43
DVDD
XMODE
TIMING
MICROCOMPUTER
INTERFACE
SAMPLING
FREQUENCY
C BIT
DETECT
PA/PB
DETECT
LOCK
DETECT
SYSTEM
RESET
MODE
SELECT
INPUT
CIRCUIT
DATA
DEMODULATOR
PLL
CLOCK
IC529 SN74LV541APWR
1
OE1
2
A1
OE2
19
20 VCC
3
A2
18 Y1
4
A3
17 Y2
5
A4
16 Y3
6
A5
15 Y4
7
A6
14 Y5
8
A7
13 Y6
9
A8
10
GND
12 Y7
11 Y8
IC522 SN74LV157APWR
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
1A
1B
1Y
2Y
2B
2Y
4A
4B
4Y
3A
3B
O
S
GND
3Y
VCC
3Y
3B
3A
4Y
4B
4A
STROEE
SELECT
1A
1B
1Y
2A
2B
2Y
34
SA-WSLF1
– AMP Board –
IC101, 102, 105-107 CXD9774M
RESET 4
GND 1
GND 3
PWM BP 2
DREG RTN 5
GVDD 6
M3 7
M1 10
M2 11
DVDD 12
DREG 8
DGND 9
DGND 14
GND 16
GND 18
PWM
RECEIVER
TIMING
CONTROL
&
PROTECTION
SD 13
OTW 15
DIGITAL
REGULATOR
PROTECTION
LOGIC
OT
&
UVP
DVDD DREG
DREG
DGND
PWM AP 17
PWM
RECEIVER
DVDD DREG
DGND
DREG
GVDD
DREG
GATE
DRIVE
GVDD B
35
GVDD B
36
BST B
33
PVDD B
32
PVDD B
31
OUT B
30
OUT B
29
GND
28
GND
34
GATE
DRIVE
OCH
OCL
TIMING
CONTROL
&
PROTECTION
DREG
GATE
DRIVE
GVDD A
20
GVDD A
19
BST A
22
PVDD A
23
PVDD A
24
OUT A
25
OUT A
26
GND
27
GND
21
GATE
DRIVE
OCH
OCL
GVDD
GVDD
IC303 TK11118CSCL-G
1
2
3
5
4
VCONT
GND
NP
VIN
VOUT
CONTROL
CIRCUIT
OVER HEAT &
OVER CURRENT
PROTECTION
BANDGAP
REFERENCE
IC108, 110 CXD9788AR
S
P
Sampling Rate
Converter
Converter
DF1
DF2
Gain
Control
Filter
&
LOW
CUT
Filter
Serial Control
Liner
Interpolator
∆ ∑ Converter
XVSS
PWM
INIT/MUTE
Clock Generator
Clock Generator
(Secondary Clock System)
1
VSUBC
2
VSSR
VSSL
VSSL
VSSR
3
OUTR2
OUTL2
OUTR1
OUTL1
4
VDDR
DVDD
DVSS
VDDL
5
6
7
8
XOVSS
XOVDD
9
XFSOOUT
10 11
NSPMUTE
12
SOFTMUTE
13
PGMUTE
SCSHIFT
14
SCDT
15
SCLA
TCH
OVF FLAGR
OVF FLAGL
16
SFLAG
INIT
17
MCKSEL
18
LRCK
19
BCK
20
DA
TA
BFVDD
BFVSS
TEST
DVDD
XFSIIN
21
42
43
41 40 39 38 37
XFSOIN
36
XVDD
35
HPVDDL
34
HPOUTL2
33
HPVSSL
32
31
HPVDDR
30
HPOUTR1
HPOUTL1
29
28
HPVSSR
27
26
25
HPOUTR2
24
FSOI
23
FSOCKO
22
44
45
46
47
48
(Primary Clock System)
35
SA-WSLF1
IC801 TK11225CMCL-G
– DIAT TRANSMITTER Board –
1
2
3
6
4
CONT
GND
NP
VIN
5
GND
VOUT
CONTROL
CIRCUIT
BANDGAP
REFERENCE
CONSTANT
CURRENT
SOURCE
OVER HEAT &
OVER CURRENT
PROTECT
IC804 CXD4016R
LRCK 49
BCK 50
BCKOUT 51
LRCKOUT 52
CK12 53
CSST 54
VSS 55
VSS 58
XTCK4 60
XSM 61
MST 62
XTST 63
XRST 64
VDD
OSCI 57
56
OSCO 59
AUDIO
INTERFACE
READ-
SOLOMON
PARITY
GENERATOR
PLL
CLOCK
GENERATOR
DTIN
48
DT2 INF
47
APS
41
VSS
40
VDD
APX
39
APVGS
42
APCPO
43
38
PLVAR
37
PLREF
36
TEST5
33
TEST6
34
TEST7
35
VCOT
46
APAVS
45
APAVD
44
MODULATOR
D/A
CONVERTER
BUFFER
RAM
DAVRO
25
VDD
26
VSS
20
VDD
19
VSS
27
TEST0
28
DACK
18
DAPD
17
TEST1
29
TEST2
30
TEST3
31
TEST4
32
DAVREF
24
DAAVS
23
DAAVD
22
DAAOUT
21
CLOCK
SELECTOR
TESTMD
1
SMCK
2
IFEXMD
3
IIFSEL1
4
IIFSEL0
5
EXCKSEL
6
CHNM BL
7
DIVCODE
8
PCMID
9
EMPIN
10
VDD
11
VSS
12
SCLK
13
XSCEN
14
SWDT
15
CSOD
16
CONTROLLER
36
SA-WSLF1
• IC Pin Function Description
• SW-MAIN BOARD IC525 CXD9720BQ (AUDIO DSP)
• SW-MAIN BOARD IC525 CXD9720BQ (AUDIO DSP)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.6V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
—
Power supply terminal (+2.6V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock output to the D/A converter Not used
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal output to the D/A converter
20
BCKO
O
Bit clock signal output to the D/A converter
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the D/A converter
26
SDO4
O
Audio serial data output terminal
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input from the system controller Not used
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.6V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
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