Sony DAV-FX80 / HCD-FX80 Service Manual ▷ View online
69
HCD-FX80
IC201 MM1623BFBE
200
Ω
75
Ω
DRIVER
75
Ω
DRIVER
75
Ω
DRIVER
75
Ω
DRIVER
6.75MHz
LPF
6.75MHz
LPF
6.75MHz
LPF
13.5MHz
LPF
6.75MHz
6dB
6dB
6dB
6dB
-6dB
6dB
LPF
75
Ω
DRIVER
13.5MHz
LPF
6.75MHz
6dB
LPF
75
Ω
DRIVER
13.5MHz
LPF
6.75MHz
6dB
LPF
BIAS
CLAMP
CLAMP
CLAMP
150k
Ω
BIAS
S-DC OUT
S1/S2
VCC1
C IN
MUTE 1
CVBS IN
YC MIX
Y IN
GND1
BIAS
I/P
CY IN
CLP
CB IN
MUTE2
CR IN
VCC2
S-DC OUT
C OUT
S1
S2
CVBS OUT
GND2
CY OUT
Y OUT
GND2
CB OUT
GND2
CR OUT
GND2
28
2
1
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
150k
Ω
BIAS
150k
Ω
BIAS
150k
Ω
BIAS
IC601 MC14052BDR2
– I/O Board –
IC203 NJM2235V (TE2)
1
2
3
4
6
5
7
8
IN 1
SW 1
SW 2
VDD
VIN 3
OUT
GND
IN 2
BIAS
BUFFER
70
HCD-FX80
• IC Pin Function Description
MAIN BOARD IC506 CXD9862R (DIGITAL AUDIO PROCESSOR)
MAIN BOARD IC506 CXD9862R (DIGITAL AUDIO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal (not used)
4
LRCKI3
I
L/R sampling clock signal input terminal (not used)
5
VDDI
—
Power supply terminal (+2.5V)
6
BCKI3
I
Bit clock signal input terminal (not used)
7
PLOCK
O
Internal PLL lock signal output terminal (not used)
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
—
Power supply terminal (+2.5V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
(fixed at “L” in this set)
14
SCKOUT
O
Internal system clock output to the stream processor
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface
18
SDI1
I
Audio serial data input from the digtal audio interface
19
LRCKO
O
L/R sampling clock signal output to the stream processor
20
BCKO
O
Bit clock signal output to the stream processor
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from DSP
23 to 25
SDO1 to SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal (not used)
27
SPDIF
O
SPDIF signal output terminal (not used)
28
LRCKI2
I
L/R sampling clock signal input from DSP
29
BCKI2
I
Bit clock signal input from DSP
30
SDI2
I
Audio serial data input from the digital audio interface
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal (not used)
39
GP14
O
Row address strobe signal output terminal (not used)
40
VDDI
—
Power supply terminal (+2.5V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal (not used)
43
OE0
O
Output terminal of data output mask (not used)
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal (fixed at “H” in this set)
48
VSS
—
Ground terminal
71
HCD-FX80
Pin No.
Pin Name
I/O
Description
49
WMD0
I
External memory wait mode setting terminal (fixed at “H” in this set)
50
PAGE2
O
External memory page selection signal output terminal (not used)
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal (not used)
54
BOOT
I
Boot mode control signal input terminal (not used)
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
(fixed at “H” in this set)
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
(fixed at “L” in this set)
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface
60
VDDI
—
Power supply terminal (+2.5V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal (not used)
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+2.5V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal (not used)
87
TMS
I
Simplicity emulation data input start and end terminal (not used)
88
XTRST
I
Simplicity emulation non-sync break signal input terminal (not used)
89
TCK
I
Simplicity emulation clock signal input terminal (not used)
90
TDI
I
Simplicity emulation data input terminal (not used)
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.5V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync (fixed at “H” in this set)
117
TST2
I
Not used
118
GP11
I
(not used)
119
TST3
I
(not used)
120
VDDI
—
Power supply terminal (+2.5V)
72
HCD-FX80
MAIN BOARD IC509 M30622MGP-A14FPUO (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP SCDT/
O
Digital amp (IC108 to 110) data output
DIAT SDATA
2
DAMP SHIFT/
O
Digital amp (IC108 to 110) data output
DIAT SCLK
3
XSCEN
O
Voltage control for amp (not used)
4
SIRCS_IN
I
Sircs input
5
DSP DIN/DIR DIN
O
DSP /DIR data out
6
DSP DOUT
I
DSP data in
7
DSP CLK/DIR CLK
O
DSP/DIR clock
8
BYTE
—
Ground terminal
9
CNVSS
I
Ground terminal
10
EN A
I
Volume signal input from ENCODER (A) (not used)
11
EN B
I
Volume signal input from ENCODER (B) (not used)
12
RESET
I
System reset signal input
13
XOUT
O
Crystal output for main cock
14
VSS
—
Ground terminal
15
XIN
I
Crystal input for main clock
16
VCC
—
Power supply (+3.3V)
17
NMI
I
Not used
18
DIR ZERO
I
DIR zero in
19
DIR_CSFLAG
I
DIR csflag in
20
AC_CUT
I
Detect AC-CUT (primary power off)
21
XRST
O
XRST signal output (not used)
22
V-CONTROL
O
Voltage control output (not used)
23
DIAT CSOD
I
DIAT CSOB signal output (not used)
24
FL_CLK/LED_CLK
O
FL driver (IC803) / LED driver (IC802) clock
25
MAMUTE
I
MAMUTE Signal input from DVD RF (IC102)
26
LED LAT
O
LED driver latch
27
FL_D_OUT/LED_DATA
O
FL driver (IC803) / LED Driver (IC802) data out
28
FL_CS/STB
O
FL driver (IC803) chip select
29
12C CLK
I
12C clock input (not used)
30
12C DATA
I
12C data input (not used)
31
DVD SID/TXDI
O
SID data output to DVD RF (IC102)
32
DVD SOD/RXDI
I
SOD data input from DVD RF (IC102)
33
DVD SCO/CLK1
I
Clock signal input from DVD RF (IC102)
34
DVD XIFBUSY/RTS1
O
IFBUSY signal output to DVD RF (IC102)
35
(NO USE)
—
Not used
36
(NO USE)
—
Not used
37
(NO USE)
—
Not used
38
SEL1FS
O
DIR_SELECT/Flash Write RTS1
39
DVD XIFCS
O
DVD RF (IC102) chip select signal
40
P CONT1
O
IC REG control signal
41
EMP/FL RESET
O
FL RESET signal to FL driver (IC803)
42
SEN
O
OCSW signal output
43
MTK XRST
O
DVD reset signal
44
P CONT2
O
IC REG control signal
45
DEVICE
O
Not used
46
CE/STBY LED
O
Flash Write CE (not used)
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