Sony DAV-DZ700FW / DAV-FX1000W / DAV-FX100W / DAV-FX999W / TA-WR2 Service Manual ▷ View online
13
TA-WR2
IC110, 112 CXD9775M
RESET 4
GND 1
GND 3
PWM BP 2
DREG RTN 5
GVDD 6
M3 7
M1 10
M2 11
DVDD 12
DREG 8
DGND 9
DGND 14
GND 16
GND 18
PWM
RECEIVER
TIMING
CONTROL
&
PROTECTION
SD 13
OTW 15
DIGITAL
REGULATOR
PROTECTION
LOGIC
OT
&
UVP
DVDD DREG
DREG
DGND
PWM AP 17
PWM
RECEIVER
DVDD DREG
DGND
DREG
GVDD
DREG
GATE
DRIVE
GVDD B
35
GVDD B
36
BST B
33
PVDD B
32
PVDD B
31
OUT B
30
OUT B
29
GND
28
GND
34
GATE
DRIVE
OCH
OCL
TIMING
CONTROL
&
PROTECTION
DREG
GATE
DRIVE
GVDD A
20
GVDD A
19
BST A
22
PVDD A
23
PVDD A
24
OUT A
25
OUT A
26
GND
27
GND
21
GATE
DRIVE
OCH
OCL
GVDD
GVDD
IC111 CXD9843AR
S
P
Sampling Rate
Converter
Converter
DF1
DF2
Gain
Control
Filter
&
LOW
CUT
Filter
Serial Control
Liner
Interpolator
∆ ∑
Converter
XVSS
PWM
INIT/MUTE
Clock Generator
Clock Generator
(Secondary Clock System)
1
VSUBC
2
VSSR
VSSL
VSSL
VSSR
3
OUTR2
OUTL2
OUTR1
OUTL1
4
VDDR
DVDD
DVSS
VDDL
5
6
7
8
XOVSS
XOVDD
9
XFSOOUT
10 11
NSPMUTE
12
SOFTMUTE
13
PGMUTE
SCSHIFT
14
SCDT
15
SCLA
TCH
OVF FLAGR
OVF FLAGL
16
SFLAG
INIT
17
MCKSEL
18
LRCK
19
BCK
20
D
ATA
BFVDD
BFVSS
TEST
DVDD
XFSIIN
21
42
43
41 40 39 38 37
XFSOIN
36
XVDD
35
HPVDDL
34
HPOUTL2
33
HPVSSL
32
31
HPVDDR
30
HPOUTR1
HPOUTL1
29
28
HPVSSR
27
26
25
HPOUTR2
24
FSOI
23
FSOCKO
22
44
45
46
47
48
(Primary Clock System)
14
TA-WR2
IC113 TK11118CSCL-G
1
2
3
5
4
VCONT
GND
NP
VIN
VOUT
CONTROL
CIRCUIT
OVER HEAT &
OVER CURRENT
PROTECTION
BANDGAP
REFERENCE
IC114 SN74AHC1GU04DCKR
2
A
3
GND
1
NC
4
Y
5
VCC
15
TA-WR2
• IC Pin Function Description
RX BOARD IC107 MB89537APFM-G-654-BNDE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NC
—
Not used
2
MOD2
I
Setting terminal for the CPU operation mode Fixed at “L” in this set
3, 4
NC
—
Not used
5
MODEL
I
Setting terminal for the model
6
SIMUKE
I
Setting terminal for the destination
7 to 10
NC
—
Not used
11
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
12
AVR
I
Reference voltage (+3.3V) input terminal (for A/D converter)
13
AVSS
—
Ground terminal (for A/D converter)
14
DTVAILD
I
Data valid flag input from the RF demodulator “L”: invalid, “H”: valid
15
CSOD
I
Captor start delay signal input from the RF demodulator “H”: active
16
NC
I
Ground terminal
17
AC CUT
I
AC cut detection signal input terminal “L”: AC cut
18
NC
I
Ground terminal
Reset signal input terminal “L”: reset
19
/RESET
I
For several hundreds msec. after the power supply rises, “L” is input, then it
changes to “H”
20, 21
MD0, MD1
I
CPU operation mode setting signal input terminal
22
XO
O
Main system clock output terminal (8 MHz)
23
XI
I
Main system clock input terminal (8 MHz)
24
VSS
—
Ground terminal
25
FS2_EX
I
Not used
26
XRST_INIT
O
Reset signal output to the RF demodulator and stream processor “L”: reset
27, 28
NC
—
Not used
29
P23
I
Setting terminal for the CPU operation mode Fixed at “L” in this set
30
P22
I
Setting terminal for the CPU operation mode Fixed at “H” in this set
31, 32
NC
—
Not used
33
DAMP_PGMUTE
O
PG muting on/off control signal output to the stream processor “L”: muting on
34
DAMP_SOFTMUTE
O
Soft muting on/off control signal output to the stream processor “L”: muting on
35
DAMP_NSPMUTE
O
NSP muting on/off control signal output to the stream processor “L”: muting on
36
NC
—
Not used
37
DRIVE_RST
O
Reset signal output to the power driver “L”: reset
38
DRIVE_OCP
I
Shut down state input from the power driver “L”: shut down
39
DRIVE_OTW
I
Overtemperature warning signal input terminal Not used
40
P10
I
Setting terminal for the CPU operation mode Fixed at “H” in this set
41
LED_GREEN
O
LED drive signal output of the ON LINE indicator “H”: LED on
42
LED_RED
O
LED drive signal output of the POWER indicator “H”: LED on
43 to 47
NC
—
Not used
48
SCMODE
O
Control mode selection signal output to the RF demodulator
“L”: pin setting, “H”: serial setting”
49
NC
—
Not used
50
XSCEN
O
Serial interface enable signal output to the RF demodulator
51
DIAT_SCLK
O
Serial interface data clock signal output to the RF demodulator
52
DIAT_SWDT
O
Serial interface data write signal output to the RF demodulator
53
DIAT_SRDT
I
Serial interface data read signal input from the RF demodulator
54
NC
—
Not used
55
T_SENSE
O
Not used
16
TA-WR2
Pin No.
Pin Name
I/O
Description
56
VCC
—
Power supply terminal (+3.3V)
57
MAIN_OFF
O
Power off control signal output to the power control “H”: power off
58
V_CONT
O
Voltage control PWM signal output to the shunt regulator
59
DAMP_LATCH
O
Latch control signal output to the stream processor
60
DAMP_SHIFT
O
Shift clock signal output to the stream processor
61
DAMP_SCDT
O
Serial data output to the stream processor
62
SI2
I
Serial data input terminal
63
INT24
O
Not used
64
NC
O
Not used
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