Sony CX-JV3 / JAX-V3 Service Manual ▷ View online
54
CX-JV3
6-28.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC101 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the MPEG video/audio decoder “L”: reset
3
MUTE
I
Muting on/off control signal input terminal “H”: muting on Not used
4
DATA
I
Serial data input from the MPEG video/audio decoder
5
XLAT
I
Serial data latch pulse signal input from the MPEG video/audio decoder
6
CLOK
I
Serial data transfer clock signal input from the video CD MPEG processor
7
SENS
O
Internal status (SENSE) signal output to the MPEG video/audio decoder
8
SCLK
I
SENSE serial data reading clock signal input from the MPEG video/audio decoder
9
ATSK
I/O
Input/output terminal for anti-shock Not used
10
WFCK
O
Write frame clock signal output terminal Not used
11
XUGF (RFCK)
O
XUGF (RFCK) signal output terminal Not used
12
XPCK
O
XPCK signal output terminal Not used
13
GFS
O
Guard frame sync signal output to the video CD MPEG processor
14
C2PO
O
C2 pointer signal output to the MPEG video/audio decoder
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the MPEG video/audio decoder
16
C4M
O
4.2336 MHz clock signal output terminal Not used
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output terminal Not used
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output terminal Not used
20
MIRR
O
Mirror signal output terminal Not used
21
DFCT
I/O
Defect signal input/output terminal Not used
22
FOK
O
Focus OK signal output to the video CD MPEG processor
23
PWMI
I
Spindle motor external control signal input terminal Not used
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor servo drive signal output to the motor/coil driver
26
SSTP
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output terminal
30
SRDR
O
Sled servo drive PWM signal (–) output terminal
31
TFDR
O
Tracking servo drive PWM signal (+) output terminal
32
TRDR
O
Tracking servo drive PWM signal (–) output terminal
33
FFDR
O
Focus servo drive PWM signal (+) output terminal
34
FRDR
O
Focus servo drive PWM signal (–) output terminal
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test
37
TES1
I
Input terminal for the test
38
VC
I
Middle point voltage (+1.65V) input terminal
39
FE
I
Focus error signal input from the RF amplifier
40
SE
I
Sled error signal input from the RF amplifier
41
TE
I
Tracking error signal input from the RF amplifier
42
CE
I
Middle point servo analog signal input terminal
43
RFDC
I
RF signal input from the RF amplifier
44
ADIO
O
Output terminal for the test Not used
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
55
CX-JV3
Pin No.
Pin Name
I/O
Description
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the RF amplifier
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input terminal
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used
63
MD2
I
Digital out on/off control signal input terminal “L”: digital out off, “H”: digital out on
Not used
Not used
64
DOUT
O
Digital audio signal output terminal Not used
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the video CD MPEG processor
66
PCMD
O
Serial data output to the video CD MPEG processor
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the video CD MPEG processor
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used
“H” is output when playback disc is emphasis on Not used
69
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “L” in this set
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “L” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (16.9344 MHz)
72
XTAO
O
System clock output terminal (16.9344 MHz)
73
SOUT
O
Serial data output terminal Not used
74
SOCK
O
Serial data reading clock signal output terminal Not used
75
XOLT
O
Serial data latch pulse signal output terminal Not used
76
SQSO
O
Subcode Q data output to the MPEG video/audio decoder
77
SQCK
I
Subcode Q data reading clock signal input from the MPEG video/audio decoder
78
SCSY
I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used
79
SBSO
O
Subcode serial data output terminal Not used
80
EXCK
I
Subcode serial data reading clock signal input terminal Not used
56
CX-JV3
•
VMP50 BOARD IC801 ES3880FM (VIDEO CD MPEG PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDD3
—
Power supply terminal (+3.3V)
2
RAS
O
Row address strobe signal output to the D-RAM
3
DWE
O
Write enable signal output to the D-RAM
4 to 12
MA0 to MA8
O
Address signal output to the D-RAM
13 to 28
DBUS0 to
DBUAS15
I/O
Two-way data bus with the D-RAM
29
RESET
I
Reset signal input from the MPEG video/audio decoder “L”: reset
30
GND
—
Ground terminal
31
VDD3
—
Power supply terminal (+3.3V)
32 to 39
YUV0 to YUV7
O
YUV 8-bit video data bus output to the MPEG video/audio decoder
40
VSYNC
I
Vertical sync signal input from the MPEG video/audio decoder “L”: active
41
HSYNC
I
Horizontal sync signal input from the MPEG video/audio decoder “L”: active
42
DCLK
I
System clock signal input from the MPEG video/audio decoder
43
PCLK2X
I
27 MHz pixel clock signal input from the MPEG video/audio decoder
44
PCLK
I
13.5 MHz pixel clock signal input from the MPEG video/audio decoder
45
AUX0
I
Guard frame sync signal input from the digital signal processor
46
AUX1
I
Focus OK signal input from the digital signal processor
47
CD ACK
O
Acknowledge signal input from the system controller
48
AUX3
O
Serial data transfer clock signal output to the digital signal processor
49
AUX4
O
Interrupt request signal output to the MPEG video/audio decoder
50
GND
—
Ground terminal
51
VDD3
—
Power supply terminal (+3.3V)
52
AUX6
O
Strobe signal output to the system controller
53
AUX5
O
Strobe signal output to the MPEG video/audio decoder
54
AUX7
O
Serial data output to the system controller
55 to 62
LD0 to LD7
I/O
Two-way data bus with the MPEG video/audio decoder Data input from the program ROM
63
LWR
O
Write enable signal output terminal Not used
64
LOE
O
Output enable signal output to the program ROM
65
LCS3
O
Chip enable signal output to the program ROM
66
LCS1
O
Clock signal output to the MPEG video/audio decoder
67
LCS0
O
Chip select signal output terminal Not used
68 to 79
LA12 to LA17
O
Address signal output to the program ROM
80
GND
—
Ground terminal
81
VDD5
—
Power supply terminal (+5V)
82 to 87
LA0 to LA11
O
Address signal output to the program ROM
88
ACLK
O
Master clock signal output to the MPEG video/audio decoder
89
AOUT/
SELPLL0
O
Audio data output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
90
ATCLK
O
Audio bit clock signal (2.8224 MHz) output to the MPEG video/audio decoder
91
ATPS/
SELPLL1
O
Audio frame sync signal output to the MPEG video/audio decoder
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at “L” in this set)
92
DOE
O
Output enable signal output to the D-RAM
93
AIN
I
Audio serial data input from the MPEG video/audio decoder
94
ARCLK
I
Audio bit clock signal (2.8224 MHz) input from the MPEG video/audio decoder
95
ARFS
I
Audio frame sync signal input from the MPEG video/audio decoder
57
CX-JV3
Pin No.
Pin Name
I/O
Description
96
BCLK
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
97
PCMD
I
Serial data input from the digital signal processor
98
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
99
CAS
O
Column address strobe signal output to the D-RAM
100
GND
—
Ground terminal
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