Sony CMT-M80V / HCD-M80 Service Manual ▷ View online
41
HCD-M80
1
BUFOUT
2
STBY
3
IN
4
GND
8 BUFIN
7 VCC
6 OUT
5 OUTSAG
8dB
9dB
LPF
CLAMP
GND
VCC
IC307
BD7600FV-E2
IC304
NJM2209M
1
2
3
4
5
6
7
14
VIDEO
OUTPUT
N.C
N.C
N.C
GND
N.C
V +
CONTROL
N.C
DIFFERENTIATION
INPUT
VIDEO
INPUT
PHASE
DELAY
DIFFERENTIATION
OUTPUT
13
12
11
10
9
8
FREQUENCY
CHARACTERISTIC
COMPENSATION
LPF
SWITCH
CONTROL
SECONDARY
DIFFERENTIATION
GAIN ADJ
LOWER
LIMITER
(1)
LOWER
LIMITER
(2)
CLAMP
(
SYNC
)
CHIP
IC504
PCM1748E/2K
SCK
1 2 3
7 8
4
5
6
SERIAL
INPUT
INTERFACE
10
9
BCK
DATA
LRCK
VOUTL
V
OUTR
DGND
VDD
VCC
VCOM
AGND
FUNCTION
CONTROL
INTERFACE
SYSTEM
CLOCK
MANAGER
8 TIME OVER
SAMPLING
DIGITAL FILTER
WITH
FUNCTION
CONTROLLER
ENHANCED
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
D/A
CONVERTER
D/A
CONVERTER
OUTPUT AMP AND
LOW-PASS FILTER
LOW-PASS FILTER
OUTPUT AMP AND
LOW-PASS FILTER
LOW-PASS FILTER
ZERO DETECT
POWER SUPPLY
12
11
ZEROL
ZEROR
15
14
ML
MC
16
13
MD
SYSTEM
CLOCK
42
HCD-M80
IC506
BU2507FV-E2
14
GND
13
AO1
12
DI
11
CLK
10
LD
9
AO6
8
VCC
1
VSS
(VREFL)
2
AO2
3
AO3
4
RESET
5
AO4
6
AO5
7
VDD
(VREFH)
14BIT
SHIFT REGISTER
ADDRESS
DECODER
DECODER
D0 – D9
D10 – D13
10BIT R-2R
D/A CONVERTER
10BIT R-2R
D/A CONVERTER
10BIT LATCH
10BIT LATCH
10BIT R-2R
D/A CONVERTER
10BIT LATCH
10BIT LATCH
10BIT R-2R
D/A CONVERTER
10BIT R-2R
D/A CONVERTER
10BIT LATCH
10BIT R-2R
D/A CONVERTER
10BIT LATCH
CH2
CH3
CH4
CH5
CH1
CH6
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–VS
STBY
MUTE
NC
NC
+PWVS
OUT
–PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
– MAIN Board –
IC101, 201
TDA7296
43
HCD-M80
30
29
1
2
CCB
INTERFACE
CONTROL
CIRCUIT
LOGIC
CIRCUIT
CONTROL
CIRCUIT
26
+
–
25
24
+
–
23 22 21
20 19 18 17
+
–
+
–
–
5
+
–
–
6
7
+
–
–
8
9
10
11 12 13 14
+
–
–
+
–
3
LOUT
LBASS2
LBASS1
LTRE
LIN
LSELO
L4
L3
L2
L1
15
NC
VSS
4
TEST
VDD
ROUT
RBASS2
RBASS1
RTRE
RIN
RSELO
R4
R3
R2
R1
16
NC
CL
DI
CE
28
+
–
RVREF
+
–
LVREF
VREF
27
NC
IC323
LC75342
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
– CONTROL Board –
IC607
KA3082
44
HCD-M80
6-23.
IC PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
I/O
Description
1
VB
O
Connected to ground via a capacitor
2
IREF
O
D/A converter reference current output
3
VRF
I
D/A converter reference voltage input
4
VG
O
Connected to the analog power supply (+2.5V) via a capacitor
5
XCPSIG
O
Luminance video composite/component signal invert output terminal Not used
6
CPSIG
O
Luminance video composite/component signal output
7
CSIG
O
Chrominance video composite signal output
8
V AVD2
—
Analog power supply terminal (+2.5V) (for D/A converter)
9
V AVS2
—
Analog ground terminal (for D/A converter)
10
IVD1
—
Power supply terminal (+3.3V) (for I/O)
11
I2C CLK
I/O
Communication data reading clock signal input or transfer clock signal output terminal
Not used
Not used
12
I2C DATA
I/O
Communication data bus terminal Not used
13
GPIO0
I
Serial data input from the system controller
14
GPIO1
O
Serial data output to the system controller
15
GPIO2
O
Serial data transfer clock signal output to the system controller
16
GPIO3
I
Request signal input from the system controller
17
LVD1
—
Digital power supply terminal (+2.5V) (for AV decoder block)
18
GPIO4
I
Acknowledge signal input from the system controller
19
GPIO5
O
Chip select signal output to the system controller
20, 21
GPIO6, GPIO7
I/O
Not used
22
LVS1
—
Digital ground terminal (for AV decoder block)
23
GPIO8
I/O
Not used
24
GPIO9
O
Frequency selection signal output
25
GPIO10
I/O
Not used
26
GPIO11
O
Serial data latch pulse signal output to the digital filter
27
LVD2
—
Digital power supply terminal (+2.5V) (for AV decoder block)
28
GPIO12
O
Control signal output to the D/A converter
29
GPIO13
O
Serial data transfer clock signal output to the digital filter and D/A converter
30
GPIO14
O
Serial data output to the digital filter and D/A converter
31
IVS1
—
Ground terminal (for I/O)
32
LVS2
—
Digital ground terminal (for AV decoder block)
33
IVD2
—
Power supply terminal (+3.3V) (for I/O)
34 to 37
DRADR0 to
DRADR3
O
Address signal output to the D-RAM and program ROM
38
LVD3
—
Digital power supply terminal (+2.5V) (for AV decoder block)
39 to 45
DRADR4 to
DRADR10
O
Address signal output to the D-RAM and program ROM
46
LVS3
—
Digital ground terminal (for AV decoder block)
47
IVS2
—
Ground terminal (for I/O)
48
IVD3
—
Power supply terminal (+3.3V) (for I/O)
49 to 56
DRDAT0 to
DRDAT7
I/O
Two-way data bus with the D-RAM Data input from the program ROM
57
IVS3
—
Ground terminal (for I/O)
58
IVD4
—
Power supply terminal (+3.3V) (for I/O)
•
VMP BOARD IC505 CXD1887R (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR,
MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL ENCODER)
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